I've run into a weird error. I've been successfully calling Modelsim from the ISE gui for the functional sim for weeks. I've finally done a P&R and when I tried to simulate the design ISE generated a testbench.tdo file that has the wrong UUT. It is not the top module in my hierarchy. The modulename_timsim.vhd and sdf files seen correct. I went in and edited the .tdo file to put the correct The modulename_timsim.vhd and sdf files and Modelsim started up and simulated correctly. I tried deleting the .tdo file and regenerating the timesim.vhd file again but to no avail. It just occurred to me as I was writing this that I'll have to look at the hierarchy of the timesim.vhd file it generated. Does anyone know how ISE generates the .tdo file. Where is it getting the wrong top level module from?
Thanks
CTW