I was curious if there is much difference in leakage current or other heat-effecting conditions between FPGA logic blocks that are programmed and those that are idle.
Presumably, logic that is switching is generating heat. However, is there an optimal programming state for inactive gates in order to reduce heat?
In particular, if I have 8 ARINC-429 channels in my FPGA, but the current configuration of the system only uses 2 of them, would it be beneficial (from a heat point of view) to have a different bitstream that only has
2 ARINC-429 channels?-bh