Temperature considerations of inactive logic blocks

I was curious if there is much difference in leakage current or other heat-effecting conditions between FPGA logic blocks that are programmed and those that are idle.

Presumably, logic that is switching is generating heat. However, is there an optimal programming state for inactive gates in order to reduce heat?

In particular, if I have 8 ARINC-429 channels in my FPGA, but the current configuration of the system only uses 2 of them, would it be beneficial (from a heat point of view) to have a different bitstream that only has

2 ARINC-429 channels?

-bh

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bh
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You cannot reduce leakage current by changing the bitstream. Peter Alfke

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Peter Alfke

You mean Static leakage, in current Xilinx FPGAs ?

It is not a bad idea, to have as well as Clock Enables and clock distribution management, a similar thing with Core Power ? Other fields do this already to mitigate the power hits of the finer processes, and it would cost a little die area. It would not surprise me to see this on future parts.

Then, the P&R software could have two more targets : Minimum Clocked Power, and minimum Static Power :)

To answer this specific question, you should create two valid designs, and measure them. Depending on where the inactive channel CLOCKs are gated, (and even the physical placements) you could expect to find a power saving.

-jg

Reply to
Jim Granville

I was addressing todat's situation in all FPGAs, since none has Vcc control. In the future one can think of many selective power-down solutions, but they have their own little problems and trade-offs. I just answered an applications question. Peter Alfke

Reply to
Peter Alfke

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