Are you saying that the synthesis uses only C-cells, or C-cells in
> addition
> to R-cells. Your fclr and fset inputs require gates, so an R-Cell
> could not
> implement the logic by itself. I think in Xilinx you would use a LUT
> as
> well as the adjacent flip-flop to implement each bit.
Well it uses ca. 4 C-cells for each bit. The 8-bit redundant register (requiring 24 single FFs) uses 98 or 100 C-cells! It is way too much...
In fact the Actel documentation ("Actel HDL Coding Style Guide" -
formatting link
page 87) states: [...] Asynchronous Preset and Clear This is the most problematic register for the ACT 2, XL, DX, MX, SX and ACT 3 architectures. You can only use one cell (the DFPC cell) to design an asynchronous preset and clear register. The DFPC uses two CMODs to form a master latch and a slave latch that together form one register. This uses two CMODs per register and offers no logic combinability with the SMOD. The DFPC requires more setup time and no combinability. The net timing loss can often be as high as 10ns. Actel recommends that you do not use any asynchronous preset and clear registers on critical paths. Use a synchronous preset with asynchronous clear or a synchronous clear register instead. You can use an asynchronous preset and clear register if it does not affect a critical path or cause high utilization in the design. [...]
However the above contradicts to the R-cell layout shown in the datasheet, which I've quoted in the first post - the FF in R-cell is equipped with independent Clear and Preset. However, when I've inspected different synthesized project, I've seen that always one of them was tied to ground, so maybe they are not completely indepentent?
Well, if it is impossible to build such flip-flops with the R-cells, and if the price of RT parts is unacceptable, what are the alternatives? Does anybody know if there are some data about radiation hardness of eg. Altera Hardcopy devices??? I've tried to google them, but found almost nothing...