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TCL testcase in Modelsim.

Hello,

Does anybody have experience on writing TCL testcase in Modelsim? I only have VHDL simulation license of Modelsim, I used to write both testbench and testcase in VHDL. But I feel VHDL is not that nice to implement testcase.

So I am thinking to implement my testbench in VHDL, and write the testcases in TCL for my next project. Of course the verification should be self-checking.

Does it sounds feasible? How is the simulation speed? Can anyone give me some reference? Thanks in advance.

-Best Regards Jim

Reply to
bigyellow
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I would consider a testcase to be a subset of a testbench. I would also consider vhdl to be 'nicer' than TCL for this purpose. See

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-- Mike Treseler

Reply to
Mike Treseler

Yes, I also did the same thing. Wrote hundreds of procedures and then use them in different testcases. I think it is quite complicate. For example, I need logics, procedures etc to control the behavior of testbenchs, but in modelsim, I can do it by forcing the register's value directly, rather than use vhdl procedure to write the register.

I am starter of tcl, and I just wonder to know if using TCL could simplify the verification process.

-Jim

Reply to
bigyellow

Once I have virtualized a register load with a vhdl procedure, calling this procedure is no more difficult than a tcl force command. It also matches what the firmware has to do. If vhdl can't cover a verification, neither can the system software.

TCL is well suited to orchestrate multiple OS commands and vsim runs if python or sh is not available. I would not use it directly for bit level stimulus or verification, but some do.

-- Mike Treseler

Reply to
Mike Treseler

Then you should get to know VHDL better. VHDL offers a lot of high level constructs and ways to write behavioral code. If you come from an RTL back ground, then the hardest thing I suppose is switching to a behavioral mind set. You are freed from all limitations otherwise imposed to you by the synthesizer.

I would not go into that path. As others already said: it is not portable. And VHDL offers much more than Tcl.

--
Paul Uiterlinden
www.aimvalley.nl
e-mail addres: remove the not.
Reply to
Paul Uiterlinden

But in general a VHDL testbench is not limiting the simulation speed, the design is. The testbench is written in a behavioral way, which simulates much faster than the RTL code of the design.

--
Paul Uiterlinden
www.aimvalley.nl
e-mail addres: remove the not.
Reply to
Paul Uiterlinden

Dear Jim,

Have you solve the problem? I also had such idea. Our method is like yours. Testbench written in VHDL (I am using System Verilog now), and the test case are text based command. I want to add TCL script in the test case.

I think we are using an advanced method in the simulation (verifiation). Hope we can keep touch.

My email addres : jeffery snipped-for-privacy@hotmail.com

Thanks

Jeffery

Reply to
jeffery_dong

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