Is task in verilog equivalent to procedure in VHDL? I am trying to convert a verilog file to vhdl.
Verilog =>
// string data type reg [8*4:1]a; reg [8*255:0]b;
VHDL =>
Is the above equivalent to variable a : string(1 to 8*4) variable b : string(1 to 8*255)