I've been interested in using SystemVerilog for quite some time now I don't really know if the tool support is there yet.
XST doesn't (yet?) support SystemVerilog so I tested Precision instead. Unfortunately it didn't seem to work that well. Some constructs were supported but I couldn't get interfaces to work reliably.
Is there any tool available that does support SystemVerilog synthesis for Xilinx FPGAs today?
I'm mainly interested in these features (for synthesis that is):
- Interfaces (This is very high on my wishlist)
- always_comb/always_ff
- The logic net type (I really dislike the wire/reg confusion)
/Andreas