hi everybody
I'm learning two ways of describing a system .... Either by using systemC and the other way, VHDL !
What are the differences, the real advantages of one compared to the other ?=20
thx T=F4F
hi everybody
I'm learning two ways of describing a system .... Either by using systemC and the other way, VHDL !
What are the differences, the real advantages of one compared to the other ?=20
thx T=F4F
Without knowing either real well, at least VHDL can be used to synthesize HW with tools mentioned here. I never heard of systemC synthesis but I bet it simulates faster.
my 1c
Heres a code comparison.
If you already know C++ systemC might be easier to learn for simulation models.
If you are interested in synthesis, or if you don't know either language vhdl might be a better choice. SystemC synthesis does a conversion to vhdl (or verilog) in any case, so it might be a good idea to learn both.
-Mike Treseler
thanks a lot for the comparaison sheet, it's very interesting !
I'm also interested in synthesis because I use vhdl essentially for system synthesis. So my question is : what the interest in learning SystemC ?
In the industrial world, which one is the most used ?
The attraction is that you can run simulations using only a C++ compiler. The downside is no direct synthesis and immature tools. The systemC standard is at version 1.0
vhdl and verilog.
-- Mike Treseler
SystemC is at version 2.1 with a free library:
Free with a $4000 membership.
-- Mike Treseler
You don't have to be a member. You just have to be a "licensee". I certainly didn't pay $4K.
Hi,
VHDL/Verilog are good for defining an FPGA/ASIC, SystemC is good for defining a System containing more (multiple ASICs, SW+HW,...).
In SystemC you won't be able to squeeze a design for speed, area and power like you do in VHDL/Verilog. In VHDL/Verilog you die, if you like to simulate linux booting on your CPU-Core. In fact you have to choose the one you need, but it's most likely, that you use both, if you need SystemC, while there are enough designs left, which need only VHDL/Verilog. BTW VHDL is IMHO a bit better on closing the gap between System and ASIC, but SystemVerilog is a bit closer on system modeling than VHDL.
bye Thomas
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