system verilog

i want to use system verilog for system modelling,kindy tellme how can i use that and how can i write code suppose for example i want to make model of and gate with test benches how do i compile my code which compiler is required? tell me the whole details mamta

Reply to
mamtachalana
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I am not aware of any SystemVerilog support for FPGA flow. And not much is available for ASIC design either yet although most all the big EDA guys are committed to supporting it.

You should be looking in the comp.lang./verilog, alot more people there know about it. Also google for systemverilog to get the latest news and status.

Q do you really need sv at all, the new stuff is really for high level verification.

If you only want to model gates, you only need plain verilog.

regards

johnjakson_usa_com

Reply to
john jakson

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