System Generator

Does any buddy knows what are the steps to bring a system generator model in to VHDL top level module. I have a simple logic implemented in system generator and i use NGC netlist to create netlist and Vhdl code fo that model. Now i i would have a top level model how can i bring sysgen model in it. I know a little that i have to instantiate it in top level but any one can give me any example...

Thanks

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Fizzy
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