SysGnen 6.2: problem with DDS module

Hi all, I created a system generator file to use the DDS core, and when I try to simulate, it gives the following error: Input width should be equal to accumulator width. I created the DDS module with phase increment as "register", and phase offset constant, and output width set to 27. The number entering the DDS Data port is also 27 bit. What's going on, and what does the error mean? Thanks, Vadim