Hello,
I want to synthesize my VHDL code targeting an ASIC design, and I want to do this using as primitive elements only NAND gates and d-flip- flops.
So, basically what I think I have to do is either build a new library for the synthesizer containing only what I want to use, or use an existing library excluding all the "building-blocks" I don't want. I should make clear that I am only interested in getting an RTL schematic of my synthesized-design, and not getting any back- annotation information.
Does anyone have any suggestions on how to do this?
I am using Mentor Graphics tools (Leonardo, Precision) but if someone can suggest a solution even with Cadence tools (or even the rtl- schematic viewer of xilinx-ISE) it would be greatly appreciated.
Thanks in advance
George (mail: giorgos.puiklis aat gmail.com )