Synthesizing big RAMs

That is 1Mbit, and plenty of Xilinx parts have that much blockRAM. That is "only" about 32 V5 blockRAMs, and every V5 part has at least that much. If you just want a large RAM with a single access point, it's often best to use an external RAM and a smaller FPGA. The blockRAMs are designed for parallel processing. -Kevin

Incorrect. Most Xilinx FPGAs have 18 Kbit block RAMs. There are parts with 64 or more block RAMs, for instance, all but the smallest Virtex-4 parts, most Virtex-5 parts, Spartan 3 XC3S4000 and up, or any Spartan-3A DSP,

I answered your code on the comp.vhdl group. I think what you don't understand is that if your dout statement is outside your clk block, you will get what Xilinx calls an unregistered output.

For some reason, Xilinx decided that unregistered RAM is distributed, that is, it is made up indivivdual registers scatered throughout the fabric.

If the output is registered, on the other hand, then ISE will drop your RAM into BRAM or Block RAM, which is much more abundant in most Xilinx parts, and also you will not task the synthesis tool to scatter and then route your RAM, which is very time consuming.

Try this for more memory models:

Brad Smallridge AiVision

I had thought that the requirement for inferring BRAM was:

1) Either register the read address, or the read data output 2) register the write into the ram signal/variable

So that not registering the "dout" signal would be OK, as long as the read address signal was registered.

Let me give a better explanation: Xilinx BlockRAMs are synchronous blocks. "Nothing happens without a clock". That means, the data output of a read operation appears at the RAM output as a result of the same clock edge that registered the address and the Enables. This is what happens in the "latched" option. There is also a "registered" option, where the output data only appears as a result of the subsequent clock edge, internally pipelined. It's the usual trade-off between performance and latency. When the designer specifies combinatorial RAM read operation (without a clock), the synthesis tool has no choice, it can only select the distributed LUT-RAM function, since the BlockRAM inherently cannot possibly perform a combinatorial read.

Specifying combinatorial vs clocked read operation has a big impact on the design implementation... Peter Alfke

Dave, you are right.

Looking back at the link I quoted, most of the dout assignments are outside the clk block. I am not sure when or why I started putting dout inside the block. I am pretty sure that I never registered the read address lines.

So I guess I have no answer for Xin. There is a switch, however, in one of the synthesis process properties. Maybe he inadvertently turned off his BRAM.

Brad Smallridge AiVision

yes brad, but now I solved the problem. I was using a small fpga, and it hadn't enough block rams. I've chose another model and now all works well.