Hello all, I was experimenting a design with V4 lx60. Synthesizer is synplify 8.0 and xilinx ISE7.1 for PAR. Two clocks to the design clk and ckl4x. But in the pacakage pin assignment tool lot of signals are listed under the global resource. Locked clk and clk4x to global clk IO. But at the maping stage the MAP is telling to LOCK the clock resources which i think is this extra created global signals. Why the synthesizer is creating extra signals which behaves like clocks. Also if i apply a timing constrain to the internal signal this problem will not be there at the mapping stage. But the PAR will never complete. After about 6 hrs work it says that the design is unroutable. Is this because of this extra global signals. But if i use lx200 instead lx60 there is no problem in the above two step and MAP and PAR completes successfully. How can i eliminate creation of such global clocks by synthsizer. regards Sumesh V S
- posted
18 years ago