synthesizable RAM problem

Hello

Currently I am implementing my own IP which I wanna add to the FSL of the Microblaze soft processor. But unfortunately I have problems with the RAM I programmed. Although it is fully synthesizeable it doesnt work the way I want it to on the FPGA. In the simulation it looks good to me, so probably there is some syntax I use which causes problems on the FPGA. Here is the VHDL Code:

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;

-------------------------------------------------------------------

-- START: Memory

------------------------------------------------------------------- entity memory is generic (width : integer); port (clk : in std_ulogic; rst : in std_ulogic; data_in : in std_ulogic_vector(31 downto 0); wr_addr: in std_ulogic_vector(7 downto 0); wr : in std_ulogic; rd1_addr :in std_ulogic_vector(7 downto 0); rd1 : in std_ulogic; data1_out:out std_ulogic_vector(31 downto 0) ); end memory;

architecture rtl of memory is

type reg_type is array (0 to 3) of std_ulogic_vector(31 downto 0); signal reg_file : reg_type;

begin

write : process(clk,rst,data_in,wr_addr,wr) variable x_int : integer; begin if rst = '1' then reg_file(0) '0'); reg_file(1) '0'); reg_file(2) '0'); reg_file(3) '0'); x_int:=0; else if clk'event and clk = '1' then x_int:=to_integer(unsigned(wr_addr)); if wr = '1' then reg_file(x_int)

Reply to
Philipp Grabher
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Patrick,

See comp.lang.vhdl for a recent critique of a very similar design.

--- Mike Treseler

Reply to
Mike Treseler

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