Synthesis of DSP algorithms

Hello,

Since any datapath design is essentially a control statemachine, I was wondering about the following: Say I have a certain DSP function to implement. If I'm to specify literally every single statement to be carried out in a certain state and carry on to fill the whole datapath control statemachine, do you think that the synthesizer (and subconsequently the implementer) will do a good job in extracting and minimizing the design as a whole. I tried it out on fairly simple designs (FIR filter), and apparently there isn't much difference in terms of logic occupancy nor in terms of timing compared to an equivalent design based on Xilinx core generator (ISE 8.1). I know that an FIR filter case is far from being a faithful benchmark and this is basically why I'm seeking counselling on this issue from the gurus in here.

If this turned out to be promising, I intend to write a tool to basically fill in a template statemachine with desired tasks (accounting for everything including pipelining) and let the CAD tools worry about the rest. Would be great to hear opinions on this.

Many thanks,

Cheers,

-Manny

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Manny
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