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Synthesis changes after ISE upgrade

I just upgraded ISE 6.3.03 to 8.1 and already I am experiencing varying synthesis results. For one thing I do not infer FSM any more and the next states are bunch of latches. There is unexpected ROM inference though. This design is synchronous and works fine in ver 6 both at behavioral and gate level.

For Post Route simulation, under the testbench target is UUT as expected, but with a "?". When I add the *_timesim.vhd I get duplicate design unit error.

I don't know whether Xilinx went thru a major overhaul for XST engine after ver 6. Please advise about getting consistent results across the board.

Thanks. YZ

Reply to
Yaseen Zaidi
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Yaseen Zaidi schrieb:

unfortunatly Xilinx software just gets more and more buggy every major release.

therefore if you have some project working on some specific ISE major release you must keep a working copy of that ISE release as using newer major release may couse any amount of unexpected results.

Sorry Xilinx. This is the way it is. I have been suggesting to upgrade to 8.1 (both ISE and EDK) but recently I have had REALLY REALLY bad trouble only because I dont have ISE 7.1 installation anymore and one important PCI-X design just refuses to work at all on 8.1 So I need to re-install 7.1 again just for that one project.

I am still saying that upgrade to 8.1 is a must, but it is equally important to keep working parallel installations of 6.x and 7.x tools (both ISE and EDK).

antti

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Reply to
Antti

I have got the same problem,too. After installing ISE 8.1i, I found some of my projects created in 7.1i can not be opened again.

Reply to
StanleyLee

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