synthesis...

There is nothing magical with for and while loops in a synthesized design. The synthesizer will simply unroll the loop for you. If you know this you should easily be able to tell if a for loop is applicable in your particular case.

For example, if you would like to write something like this in Verilog a for loop is very suitable to do it:

// Bit reverse the signal: always @* begin foo[0] = bar[63]; foo[1] = bar[62]; foo[2] = bar[61]; // Kind of boring to write this without a for loop...

However, lets say that you have an array with 512 values in a memory and you want to calculate the sum of all values:

always @* begin sum = 0 for(i=0; i < 512; i = i + 1) begin sum = sum + mem[i]; end end

This is going to be hugely expensive in terms of hardware to implement as you will end up with 512 adders and force your memory to be implemented using flip-flops instead of a blockram. In this case it is probably a much better idea to write a small state machine to sum the values. It will take around 512 clock cycles unless you do something clever like reading several values at a time, but the footprint will be much more reasonable.

/Andreas

Reply to
Andreas Ehliar
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hai,

I learned from the Xilinx manual that for,while do statements are synthesized in XST..

I would like to know how these statements(for,while,do while) are implemented as logic design(EDIF and constraints) in FPGA device?? .

Though FOR loop is synthesizable , it is always advised that FOR loops are not to be used in RTL coding. This is because it consumes lot of resources (like area etc)whether XST will not optimize it before targetting to FPGA device???

As wait() is not supported for synthesis wat should i use instead of wait()??

regards, faz

Reply to
fazulu deen

Of course, and I believe I wrote in my original post that a for loop will simply be unrolled. My example was merely meant to illustrate that it is very easy to write a for loop which will be extremely expensive in hardware even though it is only a couple of lines of code. This is why we recommend students to avoid for-loops in our introductory courses, it is too easy to try to program instead of designing hardware. If you don't use a for loop you will immediately figure out that something is not right with your design as you are going to write 512 individual additions...

However, since you seem to have some experience with synthesizers that support wait statements I have a question for you: How should you implement a synchronous reset if you have a process like the following?

always begin

always @(posedge clk); // This is the state I want to end up with at reset time bar

Reply to
Andreas Ehliar

Don't confuse architecture and coding. The parallel linear adder chain will cost exactly the same hardware when coded with or without the for loop.

The same is true for the serial version (for synthesizers that support wait statements in for loops).

The decision whether to build a single cycle or multi cycle hardware has nothing to do with for loops.

Kolja Sulimma

Reply to
Kolja Sulimma

One key point with these loops is that the conditionals that define how much to loop are typically only supported for constants. Trying to do a for loop with a vector controlling your max value will probably only bring synthesis errors. Using parameters or other constant values allow you to use these loops without the synthesis complaints.

- John_H

Reply to
John_H

Just to set the record straight: What I sad was that we recommend our students in _introductory_ courses to avoid for-loops. The reason is that we have seen too many cases of students who try to program in VHDL or Verilog instead of designing hardware in VHDL or Verilog. We believe that it is probably not a good idea to teach for-loops before a student has grasped the basic concepts of hardware design using RTL language.

As I mentioned in an earlier posting, there is nothing magical about for loops, the synthesizer will simply unroll the loop. For-loops (especially in conjunction with generate) can be a great way to minimize the amount of typing.

/ANdreas

Reply to
Andreas Ehliar

hai,

As per Andreas: it is always advised that FOR loops are not to be used in RTL coding

for example:

for(int i=3D2; i>=3D0; i--) { c+ =3D a[i]*b[i+1]; };

In this case it is probably a much better idea to write a small state machine for example: case (state) first: begin c+ =3D a[2]*b[3]; c+ =3D a[1]*b[2]; c+ =3D a[0]*b[1]; state=3Doutput; end =2E......

I would like to know the difference between number of clock cycles,adders and multipliers required when "for" loop is used and "state machine" is used??

Wat is the advantage i get interms of number of clocks,resources if i have more number of states the above example is divided as 3 states instead of 1 as follows.??

case (state) first: begin c+ =3D a[2]*b[3]; state=3Dsecond; end second: begin c+ =3D a[1]*b[2]; state=3Dthird; end third: begin c+ =3D a[0]*b[1]; state=3Doutput; end

regards. faz

Reply to
fazulu deen

hai,

So u mean to say both for loop & state machine will take same number of clock cycles and resource utilization??

Wat is the advantage i get interms of number of clocks,resources if i have more number of states??

regards, faz

Reply to
fazulu deen

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