There is nothing magical with for and while loops in a synthesized design. The synthesizer will simply unroll the loop for you. If you know this you should easily be able to tell if a for loop is applicable in your particular case.
For example, if you would like to write something like this in Verilog a for loop is very suitable to do it:
// Bit reverse the signal: always @* begin foo[0] = bar[63]; foo[1] = bar[62]; foo[2] = bar[61]; // Kind of boring to write this without a for loop...
However, lets say that you have an array with 512 values in a memory and you want to calculate the sum of all values:
always @* begin sum = 0 for(i=0; i < 512; i = i + 1) begin sum = sum + mem[i]; end end
This is going to be hugely expensive in terms of hardware to implement as you will end up with 512 adders and force your memory to be implemented using flip-flops instead of a blockram. In this case it is probably a much better idea to write a small state machine to sum the values. It will take around 512 clock cycles unless you do something clever like reading several values at a time, but the footprint will be much more reasonable.
/Andreas