I have not use XST, but it is becoming more attractive. I have been using Synplify for many years now, and it works pretty well. XST has come a long way, especially now that it appears to have an RTL viewer as well as a "implementation" (gate level) viewer, which are two features I liked about Synplify (please correct me if I'm wrong about these features...I believe I read about them in XCell). I only do Xilinx work, and I pretty much stick to Verilog. I am considering dropping Synplicity and using XST.
What have people's experiences been between XST and Synplify? Is Synplify still that much better than the competition, or is XST %95 as good (or better) than Synplify?
I used Synplify for many years but I haven't used it recently. I switched to XST about a year ago when it got to the good enough level. XST improves with each release, my gut says that it's pretty close to Synplify's level at this point.
Thanks for the feedback. That's pretty much along the lines of my belief...and the high maintenance cost for Synplify is quite a deterrent to continuing using it IMO. I have one design that is running at 280MHz in a V2, and makes timing with Synplify, and a PCI-X core that makes 100MHz (I'd like to get it to make 133 though) with Synplify. I should benchmark these two and see how XST compares.
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Recently, I had a design, not really a big deal. Running at 36 and 72 MHz. XST was not able to squeeze it into a XC2S50E, but Synplify was. (~1600 LUTs to ~ 1200 LUTs). Speed was not the problem, both implementation where fast enough. But Synplify was more area efficient. We are using XST only, this was just a test with a real case.
Austin Franklin ( snipped-for-privacy@dark99room.com) wrote: : I have not use XST, but it is becoming more attractive. I have been using : Synplify for many years now, and it works pretty well. XST has come a long : way, especially now that it appears to have an RTL viewer as well as a : "implementation" (gate level) viewer, which are two features I liked about
Austin, The only area where I have any experience of Symplify is looking at autogenerated RTL schematics, and unlike my experience with ISE 6.1.xi they are correct - ISE 6.1 often misses out entire busses etc that actually exist (First time I found that I wasted half an hour thinking that synthesis was optimisng the bus away for some reason.) when displaying RTL schematics.
Also the visual presentation of the Symplify RTL schematics far suparsed that of the Xilinx tools, but then ECS (The schemtic capture/viewer tool in the Xilins ISE package(s)) is pretty grotty. (I'm being polite here)
I have Synplify 8.1, and have been using Synplify for many years. I just loaded the latest 7.1 ISE tools last night (w/ updates), and ran some tests. I found the RTL/technology viewers in ISE to be pretty decent, though I hardly tested it out much. But, from what I saw it is decent enough to strongly consider not paying $5800 for renewal of my Synplify maintenance.
I'll take a closer look and compare the two side by side. The RTL and Technology viewers of Synplify were the biggest festures I liked about the tool.
Regards,
Aust> : I have not use XST, but it is becoming more attractive. I have been
I'm having the same experience: Synplify_pro 8.1 uses 97% (map with -tx on) of an XC2V6000 (which "map" with "-tx on -timing" actually can close timing on), whereas XST 5.2 uses 102% (no -tx on). I think Synplify's CSE (or "resource sharing") is better. The difference in price between an XC2V8000 and an XC2V6000 more than covers Synplicity's fee. On the other hand, XST and Synplicity seem to be on par as far as the resulting design's speed.
One big annoyance: attributes use a completely different concept between the two tools: Synplicity, following verilog tradition, associates attributes by position within a comment before the ; of an instantiation. XST follow VHDL and associates them by name: the comment can be anywhere in the file. But now that I have my conversion script, this is no big deal. XST uses data_bus and Synplicity uses data_bus[1]. XST flattens the hierarchy, Synplicity doesn't (earlier versions used to). All of this makes the .ucf file fun.
We are not using later versions of XST due to answer record #16808 (casex doesn't always make correct code)- I'd like to try 7.1i, but it wont work on RedHat 7.3. Synplify 8.1 (their latest) does work in RedHat 7.3. Also code errors which XST 5.2 allows cause XST 6.1 - 6.3 to core dump- which makes it difficult to find the error. Note that we have to run XST 5.2i in wine (but we then run place & route with 6.2isp3).
Other issues: synplicity runs about 33% faster, but sometimes for larger designs it is much faster. I think we are hitting some exponential time algorithm in XST.
The error reporting from Synplify is much better than XST:
I was recently evaluating Synplify Pro as i was getting pushed to the corner in terms of area usage on the XC2VP7. This is what i found:
The comparison is not EXACT since there are probably some differences in the design constraints, but it certainly gives a fair idea. The designs are constrained for 40 MHz System Clock. (but the comparison is also valid for
80 MHz, as in my opinion, either frequency is on the low end of what these devices can handle).
Also, not ALL the error checking is implemented.
Resource ISE6.3sp3 Synplify
8.0
Flip Flops 4170
3945
4 Input LUTs (Logic) 5503 3923
4 Input LUTs(Route-thru) 814 309
4 Input LUTs(Total) 6318 4232
Occupied Slices 4075 3330
4928(Total) (Overall 15 % Savings !!!)
The comparison is not EXACT since there are probably some differences in the design constraints, but it certainly gives a fair idea. The designs are constrained for 40 MHz System Clock.
i agree its not a "fair" comparison as i was using ise6.2sp3 vs Synplify
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