I have a design which uses around 80% of an XC5V330. Synthesis to EDIF is via Synplicity and it's pretty quick.
MAP is another story. It takes around six hours and uses upwards of
6GByte (not a typo) of memory. Actually MAP claims to have used 6GB, but Linux/LSF reports that MAP has used 12GB. The machine has 16GB installed.Since the Synplicity EDIF is essentially a bunch of LUT definitions, I cannot see what MAP could be doing that needs this immense slug of memory and time. The target speed is 20MHz, which is DC on an XC5V part, and Synplicity believes it has achieved it. Are there any hints and tips out there for switches or whatever that could cut the processing resources?
For the future, Smartguide looks good. But first the design has to be stable.