Synchronous counter enable pulse length

there

have

I think this is what Peter was trying to point out somewhere along the line.

It is called the "Earle latch", which seems to find 38 hits on Google.

I have no idea if it is at all useful today. Consider that it was in the days when individual transistors were glued onto ceramic chips, with metalized wiring on them. The 360/91 was built with pretty much a discrete version of ECL.

The book I have is called "The Architecture of Pipelined Computers" by Peter M. Kogge. Copyright 1981, so you might consider it more of a history book. Still, many ideas from that time are still in use today.

-- glen

Reply to
Glen Herrmannsfeldt
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That is true. And sometimes people discover new uses for old techniques. It never hurts to learn them, because they can give you ideas on how to solve your current problems. Thanks for the information Glen. I found a lot of links to Earle Latches but no diagrams. I guess the design is too old for the internet.

Reply to
Vinh Pham

I wonder if I can get this to work:

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clock ------- | nand )------------\ data -------- \ | \ |---- | nand )---------------| nand ) -------------- out out ---- | / ---- / | nand )------------/ clockbar ----

Clock and its inverse, clockbar, apparently don't have so strict timing requirements as one might guess.

To implement AND/OR logic, the number of inputs on the final nand can be increased, and additional copies of the left middle nand can be added, also with more inputs.

-- glen

Reply to
Glen Herrmannsfeldt

It is interesting to see this discussion come up, I had never thought about doing a cout/TC (delayed) in this way!

To implement the "digital differentiator", the best I could come up with was a falling edge detector on MSB using an AND gate, an inverter and a flip-flop.

D gets the MSB and Q is ANDed with NOT(MSB). Depending on use, I guess the AND output could be synchronized (delay of 2 clocks then) if needed.

Keeping this clever TC method in mind, I'm trying to build a programmable frequency divider which uses a 20-bit loadable synchronous counter. The divisor is held in a register and is arbitrary, so no clever apriori optimizations. Currently I'm targetting a Flex6K but I'm also eyeing a Xilinx Spartan XL part.

I found if I have a counter setup to count down and decode on count == 1 which drives a DFF and is used to SLOAD the counter, I need a large number of LUTs to implement the decode/compare logic(not surprising).

To use the TC method above(counting-up), I need to load my counter with the 1's complement of my divisor.

Is the only alternative to count-down (and lots of LUTs) or count-up/TC (1's comp. of divisor) for my frequency generator to use a phase accumulator arrangement? Did I miss any other clever tricks?

Thanks in advance.

-- Jay

Reply to
se10110

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