I'm working on modifying a design in order to meet my needs and am having trouble coming up with a workable soltuion. It mainly centers around some different clock domains. This design is for a Virtex-4 SX55 FPGA.
The base design that I am starting from has 4 ADC inputs which come in with individual source synchronous clocks. They are registered using BUFIO/BUFR region clock paths and then stored into a FIFO upon receipt of an asynchronous pulse from another clock domain. The same pulse is received by all four of the ADC regional clock domains, which are all the same frequency with some fixed phase offset. Therefore, depending on when the pulse arrives at each of the domains, one, two, or three of the ADC data streams will get stored at a one clock offset from the other ones. The captures seem to occur properly ~ 50% of the time, indicating that all of the clocks are phase offset within half of the clock period.
What I'd like to do is ensure that all four of the the data streams are captured at the proper point in time every single capture. I had thought that all each of the IOB FF's to be clocked by the individual BUFIOs and then selecting one clock signal to be a BUFG which would feed all of the logic after the input buffers would be the right way to go (trial and error would decide which of the 4 individual clocks would get data that is aligned properly in time, since the phase offsets are fixed, one of the four clocks should always give proper data).
Unfortunately, when I try this design, it fails to route the new global clock path (both with and without a DCM in the chain). Does anybody have any idea what might be a good solution to this problem?
In summary: Current design (4 ADs, 4 Clocks -> 4 BUFIOs -> 4 BUFRs -> logic in 4 clock domains and 1 asynchronous capture pulse to all) Attempted design (4 ADs 4 Clocks -> 4 BUFIOs -> 1 BUFG (selected from 4 BUFIOs) -> logic in 1 clock domain so asynchronous capture pulse is guaranteed to go at the same clock for all four data streams)
Thanks for your help! John