So how does one sync data between two non-synchonous clock domains? Seems like the domain accepting the data needs to turn off the clock of the originating domain fopr at least one clock cycle. How does one express that in VHDL?
Carefully. google for metastability and/or check the FAQ.
Turning off a clock from another clock domain has metastability problems all by itself.
What sort of "data" are you interested in?
If it's just a single bit/flag, the usual approach is a pair of FFs on the receiving clock.
If it's something like a packet, the usual approach is to use a FIFO. The Empty/Full (or almostEmpty) flags have to cross the clock barrier. See above, or hope the people who designed the FIFO covered this case.
If it's just a single word of data, you can build your own FIFO that's only 1 word deep.
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This is not a simple question with a simple answer. How you synchronize data between clock domains depends on your constraints. In a general case, you need to deal with metastability on both the data and the control lines. However, I have found that the vast majority of my designs do not need extra circuitry on the data, only on the control. But that depends on your data rate relative to your clock speeds.
Here is a google link
The circuit shown in this post will let your transfer a control signal from one domain to the other while minimizing metastability and giving a single pulse. This is very useful for flagging a data transfer. If you need a handshake, you can add a FF on the right hand clock domain to the feedback path which blocks the return signal until the data has been received. Very simple and very effective.
If your data rate is higher, you need a FIFO in the data path. The control signals from the FIFO will do the hand shaking job, MT, Full, etc.
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There are several good links on exactly this subject at the end of this page in the FAQ:
One of them is a pointer to this article that came out about a week ago:
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