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Symbol names in the Design Hierarchy Window of the Xilinx Floorplanner

I am trying to analyze amount of the FPGA (V4) resources used by each of my hierarchical blocks. I am not sure if there is a better way, but I am trying to use the information available in the Floorplanner Design Hierarchy Window. However, I am having difficulty in understanding some of the symbols, which seem to be undocumented, such as MEM16, DPRAM, ISERDES (in this context). I figured that FG probably maps on a LUT, but what about FG5, FG6, etc?...Is there a document available explaining all of these?

Thanks, /Mikhail

Reply to
MM
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I wrote a perl script named xdlanalyze.pl which can analyze the amount of resources used by each hierarchical block. You can find it on my homepage at

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As for your question, I assume that FG5 is a function generator with five inputs which maps to 2 LUTs (and one MUXF5) and FG6 is a function generator with 6 inputs which will map to 4 LUTs (and two MUXF5 and one MUXF6).

/Andreas

Reply to
Andreas Ehliar

Thanks a lot Andreas, seems to be exactly what I need!

/Mikhail

Reply to
MM

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