Surge in S2? ~3 amperes at cold for a millisecond

All,

I promised I'd get back with a scope picture on S2 power on surge on Vccint.

Since I don't get to post graphics here, I will have to ask those interested to get with their Xilinx FAE to get a scope shot.

If you email me directly, I can send it also (but I might be spammed to death buy the requests .... but I will honor them if they are not too many).

Basically, the 2S60 (that I tested) has between a 3/4 ampere, and three ampere surge for a millisecond or less with a 20 ms ramp on time.

Power supply sequence doesn't matter. Temperature at cold is worse than temperature at hot, but I have but one part, so I have no idea how that holds of process.

No surges on any other supply.

The leakage follows the spreadsheet, that is there is a lot of Iccint(leak) at hot (about one ampere at 70C). In fact, by specifying the "turn-on" current required for hot, they are probably able to ignore the 3 amperes at cold (eg -- if the start up current is equal to or less than the surge, then they can be honest and claim there is no surge).

I will accept that I may have an early version of silicon, and that Paul L. correctly stated that what I have seen is fixed in future tapeouts/silicon, but that remains to be seen as well. Perhaps someone with a production device can confirm this is fixed?

Austin

Reply to
Austin Lesea
Loading thread data ...

"Current at cold is worse than current at hot" -- for the surge.

Spelled correctly, making nonsense.

Apologize for the minor goof.

Aust> All,

Reply to
Austin Lesea

You could give a web link ? [less work for everyone ?]

-jg

Reply to
Jim Granville

Jim,

I am sure I can do that, but I have to go through marketing. That will take awhile. And then, marketing will want to put there imprimatur on it.

I'd prefer to keep it in this forum to give Paula chance to reply (as I said, I may have early silicon, whose masks may have been modified to fix this behavior).

Austin

Jim Granville wrote:

Reply to
Austin Lesea

Well, I think there is a difference here. On the newsgroup we can say: "Altera Stratix-2 still has the infamous start-up current, even >2A on a 2S60, and we have measurements to prove it".

But I am not too excited about honoring them with a Xilinx website, only to have Altera then come back and claim that they finally "have REALLY" fixed it.

Gentlemen should have some constraint in washing each other's dirty laundry in public, or call each other "liar" in public, even when it would be justified, as it is in this case.

I prefer the attitude that "I am #1, and certain things are below my dignity. Let the other guy crawl around in the mud, if he enjoys that environment". But the newsgroup is like a club, where we can be more outspoken and candid... Peter Alfke

Reply to
Peter Alfke

Hi Austin,

As I previously indicated, the EP2S60 *ES* (Engineering Sample) does exhibit a surge current. This current does not exist in any other shipping SII device including the EP2S15, EP2S30, EP2S90ES, EP2S130, and EP2S180. The production EP2S60 devices, shipping later this month, also do not exhibit a surge.

The surge current issue was reflected in the Early Power Estimator 2.0. Since it was fixed, it was removed in EPE 2.1. We just realized that the errata sheet for the ES device is missing this spec; this will be rectified shortly.

specifying

ignore

less

The production start-up current is less than the operating (static) current across all temperatures.

Incidentally, our ES devices exhibit higher-than-typical static currents. I noticed in the screenshot of our chip in your power seminar that you were measuring an ES device, a fact you decided not to mention in the talk...

Austin, we have measured a bunch of production devices across process corners, voltages, temperatures, different ramp rates, different power supply start-up conditions, and on different days of the week for good measure. There is no contention-based start-up current.

Please, question our marketing all you want. But our specs are our specs. Do not accuse us of lying.

Paul Leventis Altera Corp.

Reply to
Paul Leventis

Paul,

As I said, I wanted to give you the option to respond.

Thank you for clarifying when the new material that has been fixed will be available for the 2S60, and publishing an erratum for it.

I suppose it would do no good to ask for a replacement with production silicon?

As for webinar, is the leakage going to be less for all future production parts? Sounds like the first ES lot was leakier because it was fast corner material. It is possible that it was outside the wafer acceptance critera, so I will grant you that one, too.

This ES part was within the latest spreadsheet 'maximum' specifications.

'Typical' is not something you can design to in this case.

It would be unusual not to ship material that was a bit too fast, but I grant you that if you have a hot leakage test, you could scrap these in wafer sort, and customers would never see them.

Austin

Paul Leventis wrote:

Reply to
Austin Lesea

Hi Austin,

Most ES units while leakier than typical are still within (the now reduced) production specs. Over time we gain better control over the process and hence can provide a better upper bound on worst-case leakage for production units. This was reflected in the last spec upgrade.

You don't need to convince me that looking at "typical" numbers for leakage is incorrect for most designs. Altera has published worst-case Stratix II leakage specs since day one.

Paul Leventis Altera Corp.

Reply to
Paul Leventis (at home)

[...]

But Austin could post the images on a webpage and link to them in a newsgroup message. I think a good place for such images would be fpga-faq.com but I could also place them on fpga.de

Kolja Sulimma

Reply to
Kolja Sulimma

Er, Peter,

Ok. In the same vein, what are you going to do about that slow interconnect in the V4 series then?

Paul never called Austin a liar. He merely exposed a few unmentioned facts in Austin's diatribe.

The EP2S60ES silicon is/was a power hog (ha, you should have heard the raspberries when the ES power requirements were first mentioned to the FAEs), and Altera has been exceedingly candid about this to all customers.

For the EP2S60, ES silicon is all you'll find at the moment, and it would have been better for your future credibility if Austin had immediately mentioned that your measurements had indeed been done on an EP2S60ES. Altera would have simply responded with "Yep, that's what we said. Didn't you believe us?".

Then again, the world would have missed an interesting Usenet thread...

Best regards,

Ben

Reply to
Ben Twijnstra

Ben,

But the "fixed" version isn't available till the end of the month.

All that is on the shelf today is the "broken" version.

Aust> Er, Peter,

Reply to
Austin Lesea

Kolja,

I can send the pictures to you (to post quickly), but it sounds like it isn't of any interest.

OK, I quit.

Aust> Peter Alfke wrote:

Reply to
Austin Lesea

Paul,

Are you done changing the worst case numbers?

Aust> Hi Austin,

Reply to
Austin Lesea

Just to clarify, all members except the 2S60ES have had no surge current since their introduction. And "broken" is too strong a word -- how hard is it to put a 2A supply on the board?

Regards,

Paul

Reply to
Paul Leventis

The issue of startup current surge problems has been addressed on this newsgroup before with battery-operated designs stresing seriously to supply the startup surge. Chips without inrush are so much nicer to work with.

If it's a non-problem, why would Altera bother to state on

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that "Because Virtex-4 power-up specifications are higher than its static current, it draws in-rush current spike during power-up" and show an inrush spike in the graph if there is no inrush in Virtex-4 devices just as there is no inrush in the other Stratix-II devices? Scope traces sure would be nice for *that* graph.

There are designers that need well behaved chips because they don't have the luxury of wired supplies and those engineers that have been bitten by the problems in past designs will look for the issue even if it doesn't matter as much to their current designs.

Reply to
John_H

Hi John,

this

supply

with.

I agree -- better not to have in-rush. But for most applications of high-end FPGAs (few of which are battery operated), working around an in-rush spike is not a big deal. And I should point out that if you are using a 2S60ES to actually do something, you're likely using something 2A+ for static + dynamic anyway.

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static

inrush

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would be

The V-4 plot is based on Xilinx's spec. See "Virtex-4 Data Sheet: DC and Switching Characteristics" Table 5 and compare to Table 4. For the LX60, "Typical" (nominal Si, 25C) leakage is 167 mA on IccInt while "typical" power-on current is 303 mA for IccInt. For IccAux, the numbers are 74 mA and 222 mA respectively.

I do not have a scope shot, but I trust they had good reason to publish their specs. Even if I measured a chip, there is no guarentee that unit I measured would be at the "typical" point as far as start-up vs. leakage is concerned. Whenever Xilinx gets around to publishing worst-case specs, it would be even more meaningless for me (or you) to try to capture the spec'ed behaviour on a scope, given that you are very unlikely to have a worst-case unit in your hands.

So V4 has a power-up surge. Does this mean V4 is a bad or "broken" chip? No -- at least, as far as I can tell without a published worst-case spec. Oh yeah, and the spec given is only valid if VccAux ramps before VccO (paragraph 2, page 5 of datasheet)... so I don't know what happens in arbitrary ordering, for example when you want to be hot-socket compliant.

Our point in showing this graph is that the power-on surge really doesn't matter much anyway since operating power requirements dominate. This was in response to some Xilinx FUD where they treated our previously published instantaneous current spec as if it was a "power" consumption (only valid for a constant current draw), whereas for most applications you really only care about operating power. All that graph is meant to show is that (a) Stratix II has no power-on surge and (b) even for a chip (V4) that has one, it probably isn't a dominant effect. Regards,

Paul Leventis Altera Corp.

Reply to
Paul Leventis

Austin,

No. If after further process monitoring and characterization we find that we can safely reduce our spec, we will be happy to do so. Just like our performance specs, which we have previously increased and will likely do again in the near future.

What's your point? Are you suggesting that you are better off keeping your worst-case numbers to yourself, let users design using the typical numbers, and then unleash your worst-case numbers once you are 100% certain they won't change? I wouldn't want to be the guy with the chip on my board with a 2W thermal budget when I finally find out that V4 actually could burn 2.5X the static power I'd been told.

Regards,

Paul Leventis Altera Corp.

Reply to
Paul Leventis (at home)

Paul,

I posted what the worst case was (more than a week ago).

If you are using our parts, and you want to know, your FAE can tell you everything, including plots from thousands of parts, over all the corners.

In other news --

"Virtex-4 FPGA Availability:

Virtex-4 LX25, LX60, LX100, SX35, SX55, and FX12 are shipping today. Xilinx now has a total of 14 FPGAs in production at 90nm, more than three times the number of its nearest competitor."

Austin

Reply to
Austin Lesea

Austin,

Just out of curiosity, why do you start new threads about material that was discussed in already existing ones? By my count, this is thread number 4 on the same topic; all started by you in response to an article in a different thread (correct me if my counting is wrong). Would you mind sharing the reason for this?

Reply to
Ljubisa Bajic

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