All,
I promised I'd get back with a scope picture on S2 power on surge on Vccint.
Since I don't get to post graphics here, I will have to ask those interested to get with their Xilinx FAE to get a scope shot.
If you email me directly, I can send it also (but I might be spammed to death buy the requests .... but I will honor them if they are not too many).
Basically, the 2S60 (that I tested) has between a 3/4 ampere, and three ampere surge for a millisecond or less with a 20 ms ramp on time.
Power supply sequence doesn't matter. Temperature at cold is worse than temperature at hot, but I have but one part, so I have no idea how that holds of process.
No surges on any other supply.
The leakage follows the spreadsheet, that is there is a lot of Iccint(leak) at hot (about one ampere at 70C). In fact, by specifying the "turn-on" current required for hot, they are probably able to ignore the 3 amperes at cold (eg -- if the start up current is equal to or less than the surge, then they can be honest and claim there is no surge).
I will accept that I may have an early version of silicon, and that Paul L. correctly stated that what I have seen is fixed in future tapeouts/silicon, but that remains to be seen as well. Perhaps someone with a production device can confirm this is fixed?
Austin