Hi there,
I'm trying to decide on which FPGA vendor to use for a project out of Xilinx and Altera. The one we chose will depend on a certain memory bandwidth being met so I'm interested in the maximum supported bus widths.
I'm currently heading down the RLDRAM route and have been trying to figure out how many devices are supported on the larger Virtex-4 devices. Does anyone have any experience of implementing this memory on Xilix? I've searched through the Xilinx doco and have come up with nothing concrete at all. The Altera doco clearly states the number of devices supported for each device and is generally much better quality.
Any help appreciated. SJ.