sum of array

Add them together?

Your problem is not clear. Do you have an array in memory that you need to cycle through the elements one-by-one through an accumulator? Do you have an array of registers that needs a sum through a simple adder tree? Do you need to add two arrays held in memory to get a third array?

Please clarify the help you would like.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity somme is Port ( clk : in STD_LOGIC; din : in STD_LOGIC_VECTOR (3 downto 0); taille : in STD_LOGIC_VECTOR (2 downto 0);

dout : out STD_LOGIC_VECTOR (3 downto 0) ); end somme;

architecture Behavioral of somme is type tab is array(3 downto 0) of STD_LOGIC_VECTOR(3 DOWNTO 0); signal s : tab; begin process(clk) begin if clk'event and clk ='1' then s(conv_integer(taille))

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity somme is Port ( clk : in STD_LOGIC; din : in STD_LOGIC_VECTOR (3 downto 0); taille : in STD_LOGIC_VECTOR (2 downto 0); -- clk_out : in STD_LOGIC; dout : out STD_LOGIC_VECTOR (3 downto 0) ); end somme;

architecture Behavioral of somme is type tab is array(3 downto 0) of STD_LOGIC_VECTOR(3 DOWNTO 0); signal s : tab; begin process(clk) begin if clk'event and clk ='1' then s(conv_integer(taille))

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity somme is Port ( clk : in STD_LOGIC; din : in STD_LOGIC_VECTOR (3 downto 0); taille : in STD_LOGIC_VECTOR (2 downto 0); -- clk_out : in STD_LOGIC; dout : out STD_LOGIC_VECTOR (3 downto 0) ); end somme;

architecture Behavioral of somme is type tab is array(3 downto 0) of STD_LOGIC_VECTOR(3 DOWNTO 0); signal s : tab; begin process(clk) begin if clk'event and clk ='1' then s(conv_integer(taille))

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Could it be that you haven't yet written all four elements of the array in your simulation? At start, all four elements of s are 4'hX. All four elements have to be written in order to obtain a valid dout. I am curious about the (2 downto 0) on the taille input yet array(3 downto 0) on s. Are you trying to abbreviate: if( NOT taille(2) ) then s(conv_integer(taille(1 downto 0)))

----=AD---------------------------------------------------------------------

re

for taille : i have to get an array of 4 elements so i need 2 bits to reference these elements ( the elements are represented with 4 bits ) no? that it is why i use taille isnt right?

----=AD---------------------------------------------------------------------

re

for taille : i have to calculate the sum of 4 elements so i need 2 bits to reference the elements ( the elements are for 4 bits) no?

My response isn't quoting properly so I'll top post to avoid confusion with the latest questions.

I asked about taille because the input is dimensioned with three bits (2 downto 0) rather than 2 bits (1 downto 0).

It's correct to use taille for an address but you're showing 3 bits to reference 4 elements.

for taille : i have to get an array of 4 elements so i need 2 bits to reference these elements ( the elements are represented with 4 bits ) no? that it is why i use taille isnt right?

As John_H pointed out, taille only needs to be 2 bits. In other words: taille : in STD_LOGIC_VECTOR (1 downto 0);

As for your simulation problem, your test bench needs to supply the values to be loaded into your signal "s". Otherwise, you will see X for dout.

-Dave Pollum

i dont know it still the same problem

So, tell us please: what does your simulation say the values of s(0), s(1), s(2), and s(3) are?

Troubleshooting involves breaking the problem down into smaller pieces, seeing if you can show the smaller pieces work or don't work. If you have a smaller piece that works, you can now ignore it and only need to concentrate on the smaller piece that doesn't work. You can cut that up into smaller pieces and isolate what works there.

If by s( ) you mean t( ) and all the t values are numbers according to your simulation and your resulting sum is 4'hU and 4'hX according to your simulation, it sounds like your simulator is broken.

VHDL gurus: is there *anything* that might go wrong with the addition given the libraries he has specified?

Don't think so (although my dislike of STD_LOGIC_UNSIGNED is well enough known by now).

The problem is simpler: SEQ_LOOP is an infinite loop containing an implicit state machine. The loop exits only when reset is asserted. If reset is held false, the loop continues to iterate and the final assignment is never executed, so 's' is never updated.

Could we please find the tutor (or book writer, or other "authority") who is teaching beginners to use this form of implicit state machine, and string him/her up by a rope tied around some sensitive appendage?

It makes my blood boil so much that I'm willing to post the (obvious, simple) code that works - assuming the use of NUMERIC_STD instead of STD_LOGIC_ARITH:

process (clk, reset) subtype T_chiffre is unsigned(3 downto 0); type T_tableau4x4 is array (0 to 3) of T_chiffre; variable lieu: unsigned(1 downto 0); variable t: T_tableau4x4; variable somme: T_chiffre; begin if reset = '1' then -- remettre tout à zero lieu := "00"; t := (others => (others => '0')); clk_out '0'); for i in t'range loop somme := somme + t(i); end loop; -- mettre le somme en mémoire "s" s

hi every body , i want to say thank you for all of u and this program can do the sum that i want library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity som is Port ( clk : in STD_LOGIC; reset : in STD_LOGIC; en : in STD_LOGIC_VECTOR (2 downto 0); clk_out : out STD_LOGIC; so : out STD_LOGIC_VECTOR (3 downto 0); sor : out STD_LOGIC_VECTOR (3 downto 0)); end som;

architecture Behavioral of som is TYPE TAB IS ARRAY(3 DOWNTO 0) OF STD_LOGIC_VECTOR(2 DOWNTO 0); signal t:TAB; SIGNAL s:STD_LOGIC_VECTOR (3 downto 0):=3D"0000"; begin process begin seq:loop wait until clk'event and clk =3D '1'; exit seq when reset =3D'1'; clk_out