hi, i need a whole matrix to be substracted form another in one clock cycle. and i need to store all the values of these matrices in either distributed or block RAM. i thought this is not possible with block RAM, as these have didicated ports that are fixed in width. so tried to use distributed RAM with the following verilog code.
parameter nColumns = 100; parameter nRows = 200;
parameter RAM_WIDTH = 8;
//matrix 1 data reg [RAM_WIDTH-1:0] data_1[nColumns*nRows-1:0];
//matrix 2 data reg [RAM_WIDTH-1:0] data_2[nColumns*nRows-1:0];
reg [7:0] ix = 0; reg [7:0] iy = 0;
reg[10:0] diff = 0;
always @ (start) // start will trigger the calculation begin for(ix = 0; ix < 100; ix = ix + 1) begin for(iy = 0; iy < 100; iy = iy + 1) begin diff = diff +data_1[iy] - data_2[ix]; end end end
ise webpack completed stege one systhesis of this code after around 10 minutes and did not complete the whole systhesis even after around 3 hrs.
any assistance is very much appreciated.
thank you.