Stratum4E holdover

Luiz,

It has been almost eight years now....

But, How I solved similar problems was to choose a basic oscillator that had the necessary stability requirement (less than the 3.7E-7 drift per day), and then use a DDFS (direct digital frequency synthesizer) in the FPGA fabric to generate a frequency that tracks the incoming reference. When the reference is lost, the DDFS value is no longer updated.

Then the output is whatever the last best guess of frequency and phase was, and you will drift within the specs of the oscillator.

Do not get a voltage controlled oscillator: you will not use the adjustment, it cots more money, and it ruins the inherent stability of any oscillator.

Do get an oscillator that is at least 2X higher frequency than is needed (I used 8X higher). Any frequency may be used, as the synthesizer can take a 20.000 MHz oscillator and generate exactly the 8 MHz reference you need. I used for the 2E clocks, the raw rubidium output, which was

50.2037(etc) MHz (basically every rubidium is shlightly different, but they don't drift very much Can I use the SPARTAN3E DCM to (help to) generate the HOLDOVER

Austin Lesea schrieb:

Falk,

Very good point!

Also check out ICS.

Aust> Austin Lesea schrieb:

and,

IDT also has products.

Hard to beat when it is all done for you, and costs only ~$20 for the ASSP.

Aust> Falk,

Falk, I know the Zarlink parts, but I already have the FPGA for other functions. So I want to use it. Thanks anyway.

Austin, First, thankyou very much.

I was looking "Frequency Synthesis" by Austin Lesea (what a coincidence, do You know him?) at Xcell 31. I didn't understand how can I have a jitter reduction, synthetising a higher frequency and then, dividing it down. The jitter will be the period of the incoming clock, isn't it? Now, let's say I have a 50MHz very stable clock. Using DDFS, I generate a 8.192MHz clock. The size of the adder (number of bits) will be related to the precision desired, but will not be related to the jitter. The jitter, will be 20ns (1/50MHz). To get a better jitter I can: a) use one DCM at the input clock to generate a higher input clock (N*50MHz), b) use one DCM (the DLL part) at the output clock to filter it (I'm not sure about this).

Can you comment on this?

Luiz Carlos

Sure,

The 20 ns will be there (in your example) and the only way to remove it is to filter it out.

Filters come in two forms: a PLL, and also one can use a LC tank (with a Q>100).

The LC tank is very analog, but works great. It is what I used: MSB of DDFS into a 100K resistor into the LC tank, followed by a fast comparator. Residual jitter was less than 1% from 10 Hz up.

A PLL with a long time constant is also very good. I made them with VCXO's, an RC network to the voltage control, and a XOR phase detector.

Aust> Falk,

oen_no snipped-for-privacy@yahoo.com.br schrieb:

I see. And I know that you like the challenge. But from a economic point of view its a matter of part cost (Austin quoted 20 $) versus developlment (and verification) time. And its not done in an hour if you did'nt do it before and are a 100% pro in this sector.

Yes.

Nope.

Regards Falk

Austin and Falk, thankyou again.

I'm aware of the development costs. But there is the self-satisfaction, and $20 is more than the price of the FPGA itself. Less one chip to understand, less one chip in the BOM, less space on the PCB, less one device on the JTAG chain... And I have some time.

I had another idea to diminish the jitter: Let's suppose CLKA is the 8.192MHz clock that I want to track. CLKB is a 8.192MHz clock generated by a stable oscilator. CLKB will drift from CLKA at stable rate "R" (in radians/second). So, using the DCM Phase Shifter at the "VARIABLE Phase Shift Mode", and incrementing/decrementing the phase shift value at the correct rate "R", it's possible to accomplish the holdover capability. As the Phase Shifter can have 512 steps (for the whole 2*pi radians), we can have a 1/8.192MHz/512=238ps jitter. Multiplying CLKB by N (and after the Phase Shifter, dividing it by N), the jitter will be divided by N. Can it be done?

Luiz Carlos

oen_no snipped-for-privacy@yahoo.com.br schrieb:

I doubt that you can savely multiply the 8.192 MHz clock using a DCM. The DCM is quite sensitive to incomming jitter. Its "only" designed to do multiplication/phase shift/whatever using almost crystal clear clocks comming from a XO or similar source. I think using a RC-oscillator as a clock source will make the DCM lose track. Similar thing for the integrated PLLs from vendor A. ;-) But Iam a little bit confused. Should a PLL not have MUCH better jitter tolerance?

I would use a high quality (TC)XO, multiply this using a DCM and generate my 8.912 clock. If really necessary, use a LC-tank/analog PLL/whatever to clean up residual jitter.

Regards Falk

P.S. I remember Ray asking for some properties of the phase shifter to do some similar tricks (fast setting of phase shift). AFAIK the answers from Xilins were rather disillusioning.

Falk Brunner schrieb:

One even more basic problem. The minimum input frequency for the DCM is

24 MHz.

Regards Falk

Hi Falk,

No problem, I can (will) use a 40.96MHz oscilator. And I'm using a SPARTAN3E, so the minimum clock is lower than for the SPARTAN3.

I'm not sure if changing the Phase Shifter value "on the fly" will generate any disturbance at the output. I need to learn more about the DCM.

Luiz Carlos

Hi Falk, Not if you only use the CLKFX output. Then the minimum is 1MHz. Cheers, Syms.

p.s. A DS2188 might be a cheap and easy way to attenuate your jitter. I've used them in the past.