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Stratix RAM limitations

I have a design needing a RAM which Quartus is putting into 2 VERY under-utilized Mega-RAMs instead of the M4Ks I want it to be built with. When I try to force it in the M4Ks I get the message:

Error: Can't use port A width with port B width in altsyncram megafunction

I initially instantiated altsyncram manually but when I got the error I used the memory compiler to generate it (which also let me force it in the M4Ks) and still got the same thing.

The RAM parameters are:

- Bidirection dual port mode

- Port A: Read/Write, 32-bits wide, 256 entries, 4-bits of byte enable

- Port B: Write only, 128-bits wide, 64 entries, no byte enable

- no output registers for either ports

- Each of port A and B has its own separate clock

Does anyone know why this is happening or how I can fix it? I could just string up 8 M4Ks myself but doing this manually may be painful as I expect these parameters to change a lot.

Peter

Reply to
Peter Y
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^^^^^^^^^^^^^^^ This might be the problem, from the datasheets "Mixed-port read-during-write is not supported when two different clocks are used in a dual-port RAM", see page 2-35 Stratix-II device handbook,

Just a thought,

Hans

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Hans

I should have mentioned that, but the read-during-write is set to DONT_CARE so that's not it. Setting it to OLD_DATA gives errors about that, however the error I've been getting is about the widths, and everything I've seen so far in the Handbook tells me this should be allowed. Also, this is a Stratix I part (a 1S80) that I'm targetting.

Peter

Reply to
Peter Y

Peter,

From the datasheet:

The widest bit configuration of the M4K and M-RAM blocks in true dualport

mode is 256 × 16-bit (× 18-bit with parity) and 8K × 64-bit (× 72-bit

with parity), respectively. The 128 × 32-bit (× 36-bit with parity)

configuration of the M4K block and the 4K × 128-bit (× 144-bit with parity)

configuration of the M-RAM block are unavailable because the number of

output drivers is equivalent to the maximum bit width of the respective

memory block. Because true dual-port RAM has outputs on two ports,

the maximum width of the true dual-port RAM equals half of the total

number of output drivers.

It seems to me that your 32bit port A is forcing this into MRAM. And I believe the reason it is using 2 MRAM's is due to your 128 port B.

Rob

Reply to
Rob

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