Stratix IV Announced

John,

If you want some real entertainment:

Austin

Only partially. They do not state a Typical 3.3V, but they do say this

The Abs Max spec 3.75V, V @ IO spec 3.6V

The overshoot even gives a rather strange/interesting Volts/Time plot, where 4V overshoot is allowed 100% time, but 4.45V is limited to 1% of the time.

What they do NOT say, is what happens if the 4.45V is there for 2% of the time :)

Does the device a) Fry immediately it exceeds the 1.080% time allowance ? (Their precision is impressve!) b) Think about it for a while, then Fry ? c) Suffer a gradual leakage degradation, so it exceeds the 10uA spec, after the Volt-Time threshold. d) If c) then can the device fail, or just drift out of spec, and does that drift have a limit ?

Lifetime of device ? Err ?! - They give an example of 10 years, but what should one do for a 5 year, or 20 year design life ?

There is some underlying mechanism they are trying to spec here, but would it not make more sense, to identify that mechanism, than use this rather silly (partial) table, that raises more questions than it answers ?

-jg

They've also released Hardcopy-IV, including serdes and PCI-e. Why bother with ASICs...

-- /* snipped-for-privacy@world.std.com AB1GO */ /* Joseph H. Allen */ int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)

+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p158?-79:0,q?!a[p+q*2 ]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}

Jim

They say somewhere I saw that 3.3V operation the bank voltage is recommended to be 3.0V so that the protection diodes work. It's probably less of a problem the way thay have done it than what Xilinx did in the early Spartan-3 in that it can take a 3.3V driven input. There s not a lot of margin though if all the power supply tolerances are taken into account.

John Adair Enterpo> John Adair wrote:

Joseph,

Why bother? Only because all of the 'other' solutions actually exist, where H4 is a hyper-active sales pitch for an untested capability that hasn't even been taped out yet...

Imagine all those Altera customers who designed in the Stratix III GX: all dressed up, and nowhere to go.

Using FPGAs is all about reducing risk. Converting the FPGA to an ASIC (structured or otherwise) is all about reducing costs.

No risk: Virtex 5, today, available

Lower Cost: Virtex 5 EasyPath(tm) devices, guaranteed to work, because they are IDENTICAL to the FPGA

Austin

aust> Joseph,

I believe Joseph said, "Why bother with ASICs" not "Why bother with Xilinx"

Let he who is without sin, cast the first stone.

-- Mike Treseler

Maybe Altera also shares roadmaps like you do to bigger customers, and those designers maybe do not exist... Imagine all those V4FX designers who wanted working fast tranceivers.

I would say all vendors offer surprises to customers who are using leading edge devices.

My opinion is that EasyPath is the worst of the two worlds. It has limitations in flexibility, and the possibilities with price are not that great because it is the same silicon. Better to have either the full flexibility which costs or then the lowest possible cost with no flexibility.

--Kim

Let's not turn this into a marketing slugfest. It does not take a genius to figure out why Altera was forced to embark on such a risky gamble... "We live in interesting times" Peter Alfke

And So the fudd begings to flow :) Or should we talk about sour grapes.

er

Cost - power - analog.

Jon

waiting for Spartan-4 is boring.. not interesting :(

Antti PS but times are interesting yes

I'm left wondering whatever happened to Altera's MAX III devices ? ;)

Seems to be 'missing in action' ?

-jg

I bet Lattice XP2 have killed MAX3 already the pricing for XP2 looks nice too :)

Antti

ALTERA XILIXNX QUARTUS - incremental compile ISE - NO incremental compile - Windows - Linux (for large chip, 16G of memory) - Fast compile times - Very long times (sometimes no fit unknown) - SOPC - ok to use - EDK - very hard to use - NIOS - very easy

- Microblaze - not easy

Engineers get reviewed on progress not one A vs. X I still don't understand how many questions are posted about X here. I use can use both. I like The A Company model. I don't agree that X marketing people have to do damage control here.

Sorry for the garble! the upload messed it up.

XILIXNX - ISE - NO incremental compile (2 method one from XILINX & Synplicity) (UCF's constraints not supported in Synplicity for incremental compile) - Linux for large chip, 16GB of memory required, Windows only supports 4GB - Very long times (sometimes no fit unknown, FAE's puzzled) - EDK - very hard to use - Microblaze - not easy - EasyPath - chips that failed full MFG tests. Oh yea I'll put a design in that has reliability requirement.

ALTERA - QUARTUS - incremental design (it works) - works on all families in WINDOWS - Compile times are ok! - SOPC, can use - NIOS use a lot (software engineers can plan reliable specification) - HARDCOPY - great for large chips & reduce cost where high chip count is in product.

I could go!

Engineer's get reviewed on progress not one A vs. X I still don't understand how many questions are posted here about X here. Why not make X tools obvious and watch the questions go down in this newsgroup! I use can use both. I like the Lattice CPLD's with PLL's & LVDS. I like the ACTEL also! I like The A Company model. I put the time into the design not making the design work through the tool. I watch the X FAE's struggle to resolve design issues in their tool. I could go on here about MGT & aurora using a VIRTEX2PRO and it worked on older versions of ISE and fails on a new version. Of course I had to use a newer version of ISE and Synplicity. (One of the tools was ripping something out)

I don't agree that X marketing people have to do damage control here. Why put the effort into making ISE a repeatable tool (for the same design on re-compile)!

I normally don't post! But I read this newsgroup to head off bugs. I lost control!

I would say characterizing Altera's step to be "a risky gamble" *IS* making it a marketing slugfest.

I remember when Xilinx was touting that they were one of the first adopters the then bleeding edge process geometery on the Spartan 3. They also indicated that the Spartan line would be the new ground breaker because of the need for lowest prices.

So when Xilinx uses the most current technology it is "a bold step" while Altera makes "risky gambles"?

I seem to recall that Spartan 3 had many, many issues related to the use of the advanced technology and I don't see where the Spartan line is the ground breaker for today's current technology. I guess that didn't pan out in the end, huh?

Rick