Stratix II vs. Virtex 4 - power

Another well thought out discussion. Thanks Austin! ;)

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Rick "rickman" Collins

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This whole discussion in pretty pointless. As you say, a user does not care about *how* you make the chips, just how well they work. So when Austin and Dave argue about the tradeoffs in each vendor's choice of implementations, there is *no* point. The only useful info is (1) how much it costs (not even per LUT/SLICE/ALM but the real cost of the chip you need to implement *your* design *AFTER* you get through all the sales BS a dickering [which the engineer typcially does not get into]), (2) how long the lead times are, and (3) how long it takes to get your design to run in that part with the available software.

Anything else is just noise...

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Rick "rickman" Collins

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I am confused, are you talking about Greenfield or Austin?

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Rick "rickman" Collins

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That is true. Perhaps Austin should pass his posts through an editor who will make him write out the emotional marketing stuff. Then I can see his techical posts rising to the quality level of Dr. Howard Johnson perhaps.

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Rick "rickman" Collins

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Rick,

Good words to live by.

I am concerned with:

- quiescent power (which is a direct advantage to some, not all in V4)

- performance in V4 (~5% faster in raw speed at slowest speed grade) something that is design dependent, and subject to lots of variations, so it is up to the software folks, and each individual to compare their design and make their own decision if it is a big item for them

- yield (obviously, if it doesn't yield, it is a moot story for all concerned). Yield = cost to customer. Better cost, better yield. We have 1 M units of 90nm shipped in Spartan 3 (today's press release), so no issues there.

- dynamic power savings (directly benefits almost everyone to have 1/2 the power and less in hardened block in V4 than in V2P).

No BS: we are better in all of these categories. Why claim it, if we did not have data to show it is true? No marketing, great engineering by the IC Design group, fllowed by great engineering work by our verification and charaterization lab. Am I proud of the work we do? You bet: it is our contribution to the IC Design group, and the overall excellence of the product. I will try not to be too proud of the work, and clutter up my posts.

Do I 'trash' S2? Absolutely not. Do I spread FUD? Nope (although I am guilty of subtle FUD on occason, but Peter usually keeps me honest....and I am working on it). Do I intentionally present the best, and not mention any mediocre or less than perfect stuff? Sure, don't we all? But if you want the errata list, it is something you get with ES delivery (or from your FAE prior to delivery -- who does their laundry in public? No one), and all I will say is that you can go and compare our errata with anyone else's anytime you want, and you make your own decision what is important to you.

Austin

rickman wrote:

I think you have missed my point. The things you list may be factors to the "important" features of the chips, but they do not solely determine the price, speed, availability, ... There are many other factors to consider, TOO many to make useful comparisons with the factors directly. So it is much better for the users to just compare the user issues.

As an example, I was told by a boss that they once got an FPGA vendor to give a design winning quote on a new part before that part was in production. In the short term they sold the older, pin compatible part (Vcore change only) at the *same* low price. So clearly they were not basing their bid on *known* data about yeild, die size or any other technical issues that they had measured. They were banking on their own track record and self confidence, things I can never really measure... except in their quotes.

Aust>

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Rick "rickman" Collins

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Arius - A Signal Processing Solutions Company
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I have to disagree a little.... just a little...

The occasional marketing guff isn't so much a problem... provide they don't advertise what they are doing today.. and everyday... and they point out they are marketing... so you can take it with a grain of salt.

It can be good to get their opinion of why they think they are better... or more importantly.. how they are doing things ... without going thru their usual 20 page marketing fact sheet.

But I much prefer Austin's notes from time to time... especially the little tid bits...

Simon

Now that the dust is starting to settle, I'd like to highlight the guidelines that Altera uses in involvement with this newsgroup.

1) We reactively respond to customer questions on both marketing and technical issues (if it is a marketing response, we may use a marketing person and clearly articulate the title of the poster). 2) We do not proactively start posts about our new products. 3) We respond to competitive commentary on our products, as not doing so implies agreement. 4) We refrain from personal attacks. 5) We refrain from competitive attacks unless provoked.

My responses earlier this week addressed points 1, 3, and 5 above. There clearly are additional un-written guidelines with this newsgroup, and if I have offended anyone with my overt rather than covert marketing, I offer my apology. Thank you for the newsgroup etiquette training.

Dave Greenfield Sr. Director of Propaganda & Ilk Altera Corporation

I would rather like to see technical posts on new products. Xilinx used to have a section in their data sheets on how this generation/product differs from the previous generation/product and something along those lines would probably be of interest to a large fraction of the readership of the newsgroup.

Maybe of special interest to those of us designing products while trying to keep broadly up to date on the technology...

Thanks for commenting.

It's unfortunate that the way the postings were made it appeared that only item #2 applied and that that was violated. It was pointed out late in the thread that you were (probably) responding to the Stratix-II vs Virtex-4 thread where a Xilinx professional highlighted the strong points (as he knows them) of the Virtex-4 and left the discussion of the Stratix-II to Altera. To "reactively respond" would be to post a followup to that conversation. In keeping with the train of that discussion, it would have made sense to highlight the positives of the Stratix-II - as in the August news release by Altera's Senior VP of marketing

- rather than to suggest the competition is doing things so terribly wrong which seemed to be the majority of the post. The post appeared to be competitive attacks rather than product commentary.

If you can provide reasoned insight into the Altera products and directions, your input is welcome on this board. Really.

Just please be part of a discussion - an existing thread - and keep the issues to the technical items that affect the lives of designers. Engineers see much of marketing as "fluff" so the need to contribute should be minor.

And read the newsgroup when you have a chance.

You asked for it, you get it, although it is quite long... I did this for several device generations while I was responsible for data sheets, and I did it again last month, but only circulated it within the company. Note that this is one man's slightly biased view, meant for friends and not for attack dogs...I am most impressed by the I/O and clocking enhancements, by the FIFO option, and the versatile DSP slice (cascadable multiply-accumulator). =================================================================== Virtex-4 for the Experienced Virtex-II and Virtex-IIPro User By Peter Alfke, 8-26, 2004

Virtex-4 offers about 100 innovations, and it may be heresy to compare it to its predecessors, but here is an attempt:

Technology:

90 nm triple-oxide process (three different oxide thicknesses plus different transistor thresholds) optimizes the trade-off between speed, leakage current, and I/O voltage tolerance . Vccint is now 1.2 V. Lower static leakage and dynamic current for any conventional logic implementation, and drastically lower power when using the new more highly integrated hard cores (FIFO, EMAC, DSP slices)

Structure: Radically different, ASMBL chip layout arranges functions in vertical columns, even the I/O. This allows Xilinx to introduce sub-families with optimized mix between various functions without upsetting architecture or software support. The DSP-oriented ­SX family has a much higher ratio of multiply-accumulators and BlockRAMs relative to the logic resources in the fabric. Using flip-chip packages, the ASMBL structure also offers better power distribution and lower pin inductance.

I/O: Dramatically enhanced capabilities. Each I/O pin has its own serializer/deserializer (Parallel/Serial and S/P converter). DDR interfaces need only one clock and also avoid any 1-bit latency. A 64-stage individually programmable delay line in each input can be used to adjust bit alignment or clock alignment with