Responding to comments on features and performance . . .
Stratix II Features: Altera has led the innovation to introduce high-density, high-performance FPGAs. In 2002, the Stratix family won EDN Innovation of Year award over Virtex-II Pro. This year, we introduced the Stratix II family which includes a new logic structure, a whole new set of features, and breakthrough performance. Altera is the first FPGA company to integrate dedicated SERDES and DPA circuitry into our devices for high-speed source-synchronous I/Os (LVDS, LVPECL, etc.). Altera is the first FPGA company to introduce dedicated DQ and DQS circuitry into our devices for external memory interface support (DDR, DDR2, etc.). Altera is the first FPGA company to introduce a new flexible logic structure ? the Adaptive Logic Module (ALM). Stratix II Logic Efficiency: Altera studies highlighted that had we implemented the traditional logic structure on 90nm process technology, we would have seen minimal gains on performance and cost (over 130 nm products). Stratix II devices utilize new highly flexible adaptive logic modules (ALMs) that are optimized for 90nm process technology to maximize logic efficiency and performance. The inputs of a single ALM can be flexibly divided between the two output functions, allowing wide input functions to run fast and narrow input functions to efficiently use remaining resources. Stratix II is the industry's only FPGA with such a flexible logic structure, allowing it to provide 50% faster performance and consume 25% less logic comparing to other FPGAs. Stratix II Design Security: The Stratix II devices come with both the non-volatile key and volatile key storages for design security. Altera chose to only market the non-volatile key solution because it delivers the optimal features and functionality for customers. A volatile key solution requires a battery to backup the key when the power is off, which is not ideal as it increases the cost of the solution, board manufacturing complexity and is simply less reliable. Significant protections is put in place to make sure the non-volatile key is secure within the Stratix II FPGA.
Reading poly fuses on a 9 layer 90nm process is not trivial. It cannot be done in "less than an hour". Our feature has been designed to make it as painful as possible to crack, and has been verified by independent security consultants. Since all crypto systems are crackable, including ones by our competitors, it is a question of how much money and time one is willing to spend on this endeavor.
The battery solution for a volatile key provides no data integrity. What is the purpose of having security if you can over write a "supposedly secure design" (a design that has been loaded with an encrypted bit-stream) with any other design. You can do this in Virtex
4 devices which have a security key on board. A hacker can load a new design into a device with a security key onboard without knowing the key that resides onboard. He can also change the original key itself. A poly fuse system provides data integrity since the only bit-stream you can load is the encrypted bit-stream. A hacker trying to load any other bit-stream will be not be successful in loading the device and cannot change the original design.A 256 bit key in this situation provides minimal added security beyond a 128 bit key. If you are going to spend the money to attempt cracking either Altera or Xilinx devices by reverse engineering the silicon, the entire method is dependent on how difficult you make the reverse engineering rather than the key length. Since no known method exists for cracking AES, a brute force attack is the only way to attempt to crack the key. A 128 bit key length is more than sufficient for this.
Performance Stratix II performance on average is 50% faster than Stratix performance ? details are well documented at our web-site
Dave Greenfield Sr. Director of Product Marketing ? High Density FPGAs Altera Corporation