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Strange Timing Problem

Hi all,

I have an unusual timing problem that I hope someone can help with. I've constrained the delay between flip flops within one of my VHDL macros (called COLFILT) to bo 20ns. This constraint is violated which in itself is not strange. The odd thing is that the paths violating the constraint all seem pass through another VHDL macro (called ROBAVG - variable SReg) which is in the same data path as COLFILT but the two have no direct connections.

(Note: INT_ColumnFilter is a TNM that defines all flipflops in the COLFILT VHDL macro)

Can anyone clear this up for me? What is a reference to ROBAVG doing in a timing path that should only include elements from COLFILT? I've attached an example from the timing analyser and associated code for your reference.

Thanks in advance.

================================================================================ Timing constraint: TSColFilt = MAXDELAY FROM TIMEGRP "INT_ColumnFilter" TO TIMEGRP "INT_ColumnFilter" 20 nS ; 40105 items analyzed, 14 timing errors detected. Maximum delay is 25.241ns.

-------------------------------------------------------------------------------- Slack: -5.241ns path COLFILT/FiltS to COLFILT/FiltS relative to 20.000ns delay constraint

Path COLFILT/Filt to COLFILT/FiltS contains 11 levels of logic: Path starting from Comp: CLB_R26C47.S1.CLK (from CLK180) To Delay type Delay(ns) Physical Resource Logical Resource(s)

------------------------------------------------- -------- CLB_R26C47.S1.XQ Tcko 1.372R COLFILT/FiltS COLFILT/FiltS_reg CLB_R19C31.S1.F3 net (fanout=13) 3.545R COLFILT/FiltS CLB_R19C31.S1.X Tilo 0.738R ROBAVG/Sreg0 COLFILT/C1593 CLB_R22C46.S0.G2 net (fanout=1) 2.903R COLFILT/syn7069 CLB_R22C46.S0.Y Tilo 0.738R COLFILT/N3216 COLFILT/C1585 CLB_R25C47.S0.G3 net (fanout=10) 2.337R COLFILT/C912 CLB_R25C47.S0.Y Tilo 0.738R COLFILT/C839/N27 COLFILT/C1564 CLB_R24C46.S1.F1 net (fanout=1) 1.341R COLFILT/C839/N63 CLB_R24C46.S1.COUT Topcyf 1.445R COLFILT/HPO COLFILT/C824/C6/C2 COLFILT/C824/C6/C1 COLFILT/C824/C7/C1 CLB_R23C46.S1.CIN net (fanout=1) 0.000R COLFILT/C824/C7/C1/O CLB_R23C46.S1.COUT Tbyp 0.109R COLFILT/N2915 COLFILT/C824/C8/C1 COLFILT/C824/C9/C1 CLB_R22C46.S1.CIN net (fanout=1) 0.000R COLFILT/C824/C9/C1/O CLB_R22C46.S1.Y Tciny 0.590R COLFILT/N2917 COLFILT/C824/C10/C1 COLFILT/C824/C11/C0 CLB_R24C47.S0.F4 net (fanout=1) 1.474R COLFILT/N2918 CLB_R24C47.S0.X Tilo 0.738R COLFILT/syn7390 COLFILT/C1414 CLB_R27C47.S1.F2 net (fanout=1) 1.444R COLFILT/syn7390 CLB_R27C47.S1.X Tilo 0.738R COLFILT/syn1816 COLFILT/C1411 CLB_R27C47.S0.F1 net (fanout=1) 0.404R COLFILT/syn1816 CLB_R27C47.S0.X Tilo 0.738R COLFILT/C56/N51 COLFILT/C1407 CLB_R35C56.S0.CE net (fanout=7) 2.901R COLFILT/C56/N51 CLB_R35C56.S0.CLK Tceck 0.948R COLFILT/FiltS COLFILT/FiltS_reg

------------------------------------------------- Total (8.892ns logic, 16.349ns route) 25.241ns (to CLK180) (35.2% logic, 64.8% route)

--

-- IXAcc/ITAcc are outputs to an external accumulator

-- IXSum/ITSum are input from the external accumulators

-- library IEEE; use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all;

library SYNOPSYS; use SYNOPSYS.attributes.all;

entity colfilt is port (clk: in STD_LOGIC; DataBa: in INTEGER range -32768 to 32767; DataBb: in INTEGER range -32768 to 32767; DataInReady: in STD_LOGIC; Height: in INTEGER range 0 to 31; It: in INTEGER range -256 to 255; ITSum: in INTEGER range -32768 to 32767; Ix: in INTEGER range -256 to 255; IXSum: in INTEGER range -32768 to 32767; localDiff: in INTEGER range -256 to 255; reset: in STD_LOGIC; Width: in INTEGER range 0 to 511; AccEn: out STD_LOGIC; AddrA: out INTEGER range 0 to 255; AddrB: out INTEGER range 0 to 255; DataAa: out INTEGER range -32768 to 32767; DataAb: out INTEGER range -32768 to 32767; DataOutReady: out STD_LOGIC; ENA: out STD_LOGIC; ENB: out STD_LOGIC; ITAcc: out INTEGER range -32768 to 32767; ItS: out INTEGER range -2048 to 2047; IXAcc: out INTEGER range -32768 to 32767; IxS: out INTEGER range -2048 to 2047; LoadAcc: out STD_LOGIC; stopData: out STD_LOGIC); end;

architecture colfilt_arch of colfilt is

--diagram signal declarations signal BufRead: INTEGER range 0 to 255; signal BufWrite: INTEGER range 0 to 255;

-- SYMBOLIC ENCODED state machine: FiltSide type FiltSide_type is (FS1, FS2, FS3, FS4, FS5, FS6, FS7, FS8, FS9, Init2); signal FiltSide: FiltSide_type;

-- SYMBOLIC ENCODED state machine: InputSide type InputSide_type is (Init1, IS1, IS2); signal InputSide: InputSide_type;

begin

--concurrent signal assignments

FiltSide_machine: process (clk)

--machine variables declarations variable col: INTEGER range 0 to 511; variable HPO: INTEGER range 1 to 32; variable row: INTEGER range 0 to 31;

begin

if clk'event and clk = '1' then if reset='1' then FiltSide

Reply to
Kload
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Each CLB contains eight flip flops and LUTs. A given CLB may contain logic from separate parts of your design (e.g ROBAVG and COLFILT).

The CLB "name" is taken from one of the flip flops or LUTs it contains. Thus your "COLFILT" timing paths may seem to be passing through "ROBAVG", even though there is no actual relationship between them (except that they are sharing a CLB).

BTW, use fpga_editor in future.

Regards, Allan.

Reply to
Allan Herriman

Thanks,

Yes you are right, I had a look in FPGA editor, and the two macros are sharing a CLB. This leads me to another question. Is there any way to stop the timing tools reporting on such path?? Or can I stop the place and route tools sharing CLBs between macros.

Thanks again, you help has been invaluable.

Allan Herriman wrote:

Reply to
Kload

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