Hi all: I am meet a very strange ddr controller bugs on board. since system power up. I turn on the ddr controller tester to test the DDR interface of FPGA(virtex5), after a long time run it appers just fine. but when I reset the FPGA. and run the tester again, I got errors when read back data from DDR. and I want to know does reset FPGA can cause the unstable working of DDR controller? someone can analysis it for me? Thanks and Best Regards. Buley
- posted
15 years ago