strange behavior in lpm_counter

Hi, I'm attempting to implement a 12-bit counter from a vhdl file using the lpm_counter. The output count goes something like this 125..126..255..128..129 That is, bit 8 (output[7]) goes high one clock cycle too early. The same thing happens when bit 9 (output[8]) goes high, this time the count is as follows: 251..252..509..510..383..256..257..258 Once again bit 8 goes high one clock cycle early, and bit 9 changes 3 cycles early.

At first, I noticed this and assumed there was a problem in my logic driving the counter. Using Quartus, I created a new 12 bit counter using the mega-function wizard and placed it next to my vhdl component. That counter has the exact same glitch. sclr and sset are grounded, updown and cnt_en are connected to vcc. The only input is a clock. Next I completely removed my component, and the counter still has a glitch in the output. The entire .bdf file is a counter with an input clock and output lines, the glitch remains.

Next, I created a new project, re-created a counter, and of course this one works flawlessly.

It seems that no matter what I do, I can't make the broken counter work correctly, nor break the working counter by adding my component to it.

Has anyone experienced something similar to this before? Any ideas on how to fix it?

You may need to update to the latest service pack to 4.2 From the Altera Quartus site:

"All platforms of Quartus II software version 4.1 and 4.1 service pack 1, including the free Web Edition, have an issue in the counter implementation such that when synchronous clear and asynchronous set signals are used, the synchronous clear signal logic is not generated. This issue occurs only when all three of the following conditions occur: 1.. The design targets a Stratix, Stratix GX, Cyclone, MAX II, or HardCopy Stratix device. 2.. The counter uses both synchronous clear and asynchronous set signals. 3.. The counter is explicitly instantiated with the lpm_counter megafunction in Quartus II integrated synthesis or any third-party synthesis software or in a schematic file, or is inferred by Quartus II integrated synthesis. Note: Third-party synthesis tools do not infer the lpm_counter megafunction and users of these tools will not be affected by this issue unless the user explicitly instantiates the lpm_counter megafunction in their VHDL or Verilog code."

John Cain, Power Processing, Inc., Phx, AZ - Electronic Design from Concept to Product