Storing a file onto FPGA

well if it can't be taught in schools.. shouldn't the schools get a student to write a better one ??

Simon

ISE

Others have pointed out most of the pieces.

1) With XILINX, for the actual FPGA use a BMM file and data2mem to initialize the rom contents in the bitstream. It's a pain to figure out and I last did it a year ago so I don't remember the details, but when you get it all worked out put it in a makefile that runs your table generator, updates the bit file and downloads to the FPGA.

2) For simulation, write a program that generates verilog code to initalize the memory. Yes, XILINX makes you initalize it a different way for simulation than for synthesis. Unlike apparently VHDL, verilog has an include directive, so you don't have to have your code generator recreate an actual verilog file each time, it can just spit out the file with the initialization commands. Put this in a makefile too...

This is pretty much the same problem as how to load ROM contents for a custom embedded processor (ie, one where you aren't using embedded development tools that handle the whole deal for you)

Cool! I didn't know that they had actually implemented it. Now if Synplify would follow suit, it would surely get filtered into the other fpgA tools over time. The write seemed like a logical extension, although I'm not sure how useful it is beyond writing a serial number or key to a file at compile time. Hmm, it may be a (albiet, kludgey) way to pass a propagation delay or latency back up to a higher level in the design hiearchy.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759

Alas, I've thought of this already, and it will only work for iterated synthesis. If you think about it for a second, you'll realize that the language semantics force elaboration from the top of the hierarchy down to the bottom. Generics have to be fully calculated before the subcomponents can be elaborated. If you have a generic parameter which depends on a value created during elaboration of the subcomponent, then a dependency loop will be created. This is not necessarily a bad thing, but the programmer will have to be aware of it, and make sure to stop the iteration of the elaboration of the subcomponent (at some point). I'd really like to work out a design flow where this is possible, but right now, this will require scripting a control structure to iteratively call the synthesis tool to compile the subcomponents with specified generic parameters. I think that right now, XST doesn't accept top level generics as command line arguments :-(

Bottom line: It's really tough to write code that explicitly supports multiple topologies that can automatically be explored at compile time to close timing. VHDL needs to be extended to support design space exploration, as well as to support physical timing feedback into the elaboration control structures. It'll probably take the rest of the decade to get something going with Accelera along these lines.

John McCluskey