Stopping the clock for power management

Some things to consider:

How do you exit "sleep mode"?

Does this require the clock you're stopping?

If so does the clock signal still exist in a portion of the design?

Were you considering using the FPGA to stop its own clock or use an external component? It may not be easy to stop the clock internally if you need to meet a certain phase relationship with external parts. Normally gating off a global clock will require adding some logic between the clock input pin and the global buffer (this would not be the case for parts with dynamic clock select resources, such as EC/ECP - I'm not sure if XP has these). It may be possible to fix phase problems with a PLL, but again if you stop the input to the PLL you'll need to reset it when you start the clock again. DLL's have similar issues. Also if you use either of these, you'll have problems if you need to come up operational within a few clock cycles of exiting "sleep mode".

Good Luck, Gabor

You can stop the clock, and also reduce Vcc in some cases.

However, Static Icc on these new FPGAs can be a real killer!

Look at some of the new Power control Busses / Chips appearing, that are designed to ramp the Vcc, as the clock scales. Natsemi LP5550 is one example.

-jg

The marketing term is "INSTANT ON" but us FAEs prefer "less than 1 millisecond". :)

So, yes, you can disable clocks to save some power, while the device remains active, or you can enter 'sleep mode' and save most of the power. Sleep Mode is available on the 'C' version of each device in the family. The 'C' version has an onboard regulator, so you can run the device with a single 3.3v supply. The core operates at 1.2v, (derived from the on chip regulator in the 'C' devices), we require

3.3v for VccAUX(used for thresholding and some housekeeping circuitry), and the appropriate VccIO voltages.

thanks for aking -

Michael Thomas Lattice SFAE - NY/NJ

Thanks,

I'll explore these features.

Dan.