The Xilinx core generator generates std_logic_vector(0 downto 0) on some parts like a BUSMUX. How do you "cast" this IO so that it can be connected to std_logic without errors?
Brad Smallridge b r a d @ a i v i s i o n . c o m
Brad,
if
a : std_logic_vector(0 downto 0) ;
and
b : std_logic ;
then
b The Xilinx core generator generates std_logic_vector(0 downto 0) on some
connected
connected
signal_not_vector
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