Hello,
I have a design where I need a couple of 16-bit shift registers, two bits wide. According to the "Virtex-5 FPGA User Guide", it should be possible to implement one of these in just one LUT6 in a SLICEM (as long as one doesn't need the extra flip-flop in that slice). XST does recognise them as 16-bit shift registers, but always uses two LUTs for them, instantiating two SRLC32Es.
Does anyone know how to create them in one slice?
Thanks, winscatt
It might happen automatically when your design gets larger and packing is needed for space.
-- Ben Jackson AD7GD http://www.ben.com/
I tried it, but even if I use so many SRLs that packing two of them into one LUT would be required in order to fit into the fpga and set the optimization goal in XST to "area", it doesn't work.
winscatt
Isn't the SRL16x2 a macro?
Two SRLC32Es may pack the way you expect in your V5 if they're properly constrained *and* have the same controls.
Are you familiar with RPMs? While I usually include my critical RPMs in the .ucf file there are ways to introduce them into the code itself, particularly if you're using VHDL.
How many of these SRL pairs do you have? Can you implement each pair with its own level of hierarchy? Are you using XST with Verilog or VHDL?
- John_H
I can't find it in the libraries guide.
I'm not familiar with RPMs. I don't know yet how many of the srl pairs I'll have in the end, I'm still in the early stages of the desing. And I'm using XST with VHDL.
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