Hi,
OK, left the lora chips asside for a while, so .. now back to FPGAs.
I have two olimex ice40 boards where I would like to use the onboard SRAM. The RAM chip is a samsung K5R4016V1B-10 (256K words * 16 bits).
The datasheets are here:
I am trying to interprete the datasheets to see how to use the chip. I think I understand how to read or write one word, but I still puzzled on how to do bulk-write transfers
- For read, it seams to be simple: set /WE high and /OE low (*)
1/ put the address on the address-bus
2/ 10 ns later, read the data from the data-out (*) ignoring the /CS, /LB and /UB pins to keep things simple.In bulk transfer, it is like this:
- set address 1 on the Address bus
- 10 ns later:
-> read the data of address 1 from data-out
-> (at the same time) set address 2 on the address bus
- 10 bs later:
-> read the data of address 2 from data-out
-> (at the same time) set address 3 on the address bus (etc)
- For write, to write one single word, I think it goes like this
1/ set /WE low and /OE high to go to "write" mode
-> at the same time set te address on the address bus
-> do not yet put the data on the databus (as it still in "output" mode)
2/ 10 ns later:-> put the data on the data-bus (by then, the data-bus has switched to "data-in"
3/ another 10 ns later:-> set /WE high and /OE low to leave "write" mode
But I am still puzzled on how to do a "bulk write" of data. The datasheets do not mention anything on what happens if leave the chip in "write" mode and just change the address on the address-bus (as is done for bulk-read)
It there is no seperate bulk-write protocol, it looks like a write to the chip takes 3 times as much steps then a bulk-read (3 steps compaired to one single step).
Is this a correct interpretation of the datasheet?
Can somebody who has already interfaced an FPGA with SRAM confirm or deny this. Or is there another trick on how to do a bulk-write on a SRAM chip?
Cheerio! Kr. Bonne.