SPI slave problem

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Hello Folks,
          I'm writting a slave SPI code for my FPGA and very sure that
my master is generating the right SPI but somehow slave is unable to
decode it. I've never used the verilog before so it might be possible
that something is wrong with my code. Please advice.
_________________________________________________________________________

module test_spi(led,MOSI,SS,SCK,clk);

    output    [7:0] led;

    input     MOSI, SS, SCK, clk;

    wire    MOSI;
    wire    SS;
    wire    SCK;
    wire    clk;

    reg    num = 7;
    reg    [7:0] temp = 0;
    reg    SCK_LAST;
    reg    SCK_NOW;
    reg    [7:0] led;


always @(posedge clk)

begin
  if (!SS)
    begin
       SCK_LAST = SCK_NOW;
       SCK_NOW  = SCK;
            if((SCK_LAST==0)&(SCK_NOW==1))   // check SCK is rising
edge
    begin
        if (num < 8)  // 8 bits counter
           begin
               if (!MOSI)
                  begin
         temp = (temp << 1);  //1 bit-shift and store it to temp when
receiving "0"
                  end
               else
                  begin
         temp = ((temp << 1)|8'b00000001); //1 bit-shift and store it to temp
when receiving "1"
                  end
                                                   if (num == 0)
                  begin
         led = temp;   //output to the LED on the board
         num = 10;
                  end
           end
                end
         num = num - 1;
     end
  else
     begin
         num = 7;      //reset counter and temp store
         temp = 8'b0;
     end

end

endmodule

_________________________________________________________________________


Thanks for your time.


Re: SPI slave problem
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That's almost certainly wrong.  I can't vouch for the rest.

--
Ben Jackson AD7GD
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Re: SPI slave problem


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rest.
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Thanks for prompt response! but can you elaborate a bit more?


Re: SPI slave problem

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I'm a VHDL guy, but I think it should be

reg [2:0] num;

Best regards,


Ben


Re: SPI slave problem


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but I think it should be
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ben! thanks for clue. Let me try and i'll get back to  you as i'm also
not a verilog guy;-)

Cheers


Re: SPI slave problem


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guy, but I think it should be
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and i'll get back to  you as i'm also
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0ops!  and no difference, any  idea?


--


Re: SPI slave problem

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guy, but I think it should be
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try and i'll get back to  you as i'm also
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I haven't checked in detail but move "num = num - 1;"
inside the check for SCK rising otherwise it gets decremented for
every clockcycle not every SCK cycle.

easy spot if you run a simulation ;)

-Lasse


Re: SPI slave problem
Ben Jackson schrieb:

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Initial values are ignored during synthesis. -> Create a reset for it!

Ralf

Re: SPI slave problem
Ralf Hildebrandt schrieb:
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Is it true for Verilog? Because at least XST regards initial values in
VHDL. I know some years ago, they had been ignored.

Bye Tom

Re: SPI slave problem

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As a blanket statement, Ralf is incorrect in stating that "initial values
are ignored during synthesis".  First of all it depends on the target
device:  Does the target device have a defined state at power up (CPLD) or
after configuration (FPGA).  Many devices do have such a definition.  The
second consideration is the tool set used to synthesize the bitstream from
the source code.  Some tools might not support an initial value.  It really
does not depend on the language itself but the synthesis tool.

In any case, it's not hard to find a device and tool that will support
initial values.  Ralf's advice to use a reset though is well founded.
Having something that depends solely on the power up reset state is
'usually' not sound design practice.  Again though there are exceptions, the
shift chain that one should use to generate a synchronous reset being a good
example.

Kevin Jennings



Re: SPI slave problem

snipped-for-privacy@gmail.com ha scritto:

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simply stated you should study Verilog more seriously.
Especially topics like blocking and non-blocking assignments and how
they are synthesized.


Re: SPI slave problem

Check your email.
--
Per ardua ad nauseam

Re: SPI slave problem

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Thank you for your kindly help...

I have tried your program on my board, however, I still can't get my
desired result...
I am now trying a new program on my board in a different way... to
check whether the board can receive incoming signal correctly or not...


Re: SPI slave problem
I have just succeed a little on the SPI between ATmega 128 and Xilinx
Spartan-3E.
The board now can displays my desired bit pattern.

___________________________________________________________________________________________________________________________________________

module test_spi(led,MOSI,SCK,SS,clk);

input  MOSI,SCK,SS;clk;

output  [7:0] led;

wire  MOSI,SCK,SS,clk;

reg  [3:0] num = 7;
reg  [7:0] temp = 0;
reg  [7:0] led = 0;

always @(posedge clk)    //clk ---> the clock of FPGA
    begin
    end

always @(posedge SCK)           //SCK ---> the input SCK from ATmega
    begin
        if (!SS)
            begin

                if (num < 8)
                    begin
                        if (!MOSI)
                            begin
                                temp = (temp << 1);

                            end
                        else
                            begin
                                temp = ((temp << 1)|8'b00000001);

                            end

                        if (num == 0)
                            begin
                                led = temp;
                                num = 8;
                            end
                        else
                            begin
                            end
                    end
                else
                    begin
                    end

                num = num - 1;
            end

        else
            begin
            num = 7;
            temp = 8'b0;
            led = temp;
            end
    end

endmodule


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