Hello Folks, I'm writting a slave SPI code for my FPGA and very sure that my master is generating the right SPI but somehow slave is unable to decode it. I've never used the verilog before so it might be possible that something is wrong with my code. Please advice. _________________________________________________________________________
module test_spi(led,MOSI,SS,SCK,clk);
output [7:0] led;
input MOSI, SS, SCK, clk;
wire MOSI; wire SS; wire SCK; wire clk;
reg num = 7; reg [7:0] temp = 0; reg SCK_LAST; reg SCK_NOW; reg [7:0] led;
always @(posedge clk)
begin if (!SS) begin SCK_LAST = SCK_NOW; SCK_NOW = SCK; if((SCK_LAST==0)&(SCK_NOW==1)) // check SCK is rising edge begin if (num < 8) // 8 bits counter begin if (!MOSI) begin temp = (temp