Hello,
I am a newbie to the group and FPGAs in general. We have a board with XC3S1500 FPGA on it. We use the master serial mode to configure the FPGA using a platform flash (PROM) with the FPGA providing the CCLK (confg rate -50). For debug reasons we also have the confg. signals going to a POD header.
We see that sometimes when we probe the CCLK on the POD header the FPGA fails to configure. On the scope , we could see the sequence of INIT going high, CCLK going active (clocking), DONE being low and after some time, the INIT goes high, the CCLK stops clocking but the DONE pin does not go high. We have 330 ohm pull-up on DONE pin.
If i remove the probe from the CCLK pin on the POD header the board starts-up with successful configuration.
I was wondering if anybody in the group has seen such behaviour before or may be the experts in the group could guide me on the possible issues involved.
Also, sometimes I have also seen that as the INIT goes low, CCLK goes high but does not begin to clock . In this case, a configuration failure is obvious. So, is this a problem with the chip not being consistent?
Thanks a lot in advance
Regards Nithin