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SPARTANI II - PCI target logic - what code generates burst read ?

Hello ,

I have designed a PCI target ( 32bits/33 Mhz ) and I have implemented it in a Xilinx Spartan II

It is working correctly for single data phase reads. Now I want the CPU to generate a burt read.

I have been unable to generate the CPU burst read. My code was written with DEBUG under DOS This code moves 255 16bit words from my PCI target to the CPU main memory

Mov CX, 00FF REPZ MOVSW

The code successfully executes BUT it is done as individual transactions. Each transaction is a single double word read.

There are 20 PCI clocks between reads. ( my PCI logic added 2 wait states as intended by the design )

QUESTION ONE: - what code should I use to generate a burst read ? QUESTION TWO: - why are there 20 pci clocks between reads ? ( 14 more than I would expect )

Thank you.

Sincerely Daniel DeConinck, PixelSmart Tel 416-248-4473 or 800-884-1734

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Dan DeConinck of PixelSmart
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"Dan DeConinck of PixelSmart":

If you can't mark that block as cacheable, the only thing you can do will be to use instructions, that transfer a multiple of bus size at once: mov eax,[PCI_addr] // move 32 bits movq mmx0,[PCI_addr]; // move 64 bits movps xmm0,[PCI_addr]; // move 128 bits

For writes, CPU may combine such moves.

For reads, the PCI-controller needs to know, what the final dataphase is, before that dataphase is up, I guess.

Gruss

Jan Bruns

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Jan Bruns

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