Hey,
I'm using a XC3S500E-FG320 and let the PAR choose the clk pins itself with the right IOSTANARDS, then i locked the clk pins so i know the setup should work in that configuration (because i need a lot of CLK BUFG's i thought it was the best idea to check out if it will work before i let them route the PCB) ... but then when i lock those pins (it choose itself) i get the a warning:
WARNING:Place:619 - This design either uses more than 8 clock buffers or uses more than 4 DCMs or has clock buffers locked to side-BUFG sites or has DCMs locked to side-DCM sites. The side-DCMs can drive only the BUFGs on the same side. Since side-BUFGs can drive only their half of the device and also exclude a global-BUFG from entering a clock region, it is necessary to partition the clock logic being driven by these clocks into different clock regions. It may be possible through Floorplanning all or just part of the logic being driven by the global clocks to achieve a legal placement for this design
why does it give a warning when i lock the clk pins it choose itself?
these are the clk pins it choose and the bufgmux's
NET "clk_xtal" LOC = "B9" | IOSTANDARD = LVTTL ; NET "pix_odck1" LOC = "P10" | IOSTANDARD = LVTTL ; NET "pix_odck2" LOC = "J17" | IOSTANDARD = LVTTL ;
INST "c_input_dcm/LVSD_CLK_FB_BUFG_INST" LOC = BUFGMUX_X1Y11; INST "c_input_dcm/CLKFB_BUFG_INST" LOC = BUFGMUX_X1Y0; INST "c_input_dcm/CLK_OUT_BUF_BUFGMUX_INST" LOC = BUFGMUX_X1Y1; INST "c_input_dcm/CLKFX_BUFG_INST" LOC = BUFGMUX_X2Y1; INST "c_input_dcm/CLK_OUT_int_BUFGMUX_INST" LOC = BUFGMUX_X2Y0; INST "c_input_dcm/CLKIN2_BUFGMUX_INST" LOC = BUFGMUX_X3Y3 INST "c_input_dcm/LVDS_CLKFX_BUFG_INST" LOC = BUFGMUX_X1Y10; INST "clk_xtal_BUFGP" LOC = BUFGMUX_X2Y10;
so we have one clk for one half of the device (PIX_ODCK2) and the others as global clk? what am i doing wrong?
thanks in advance,
kind regards,
Tim