Spartan3DSP TphDCM spec question

1) Why the spec calls out negative number for input holding time ? eg. TphDCM = - 0.26 ns

2) What does that means when they say

"When the hold time is negative, it is possible to change the data before the clock's active edge"

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What I read out from the above is that, the device does not require the hold time at all ...Am I correct or...?

Reply to
Mawa_fugo
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It means that the data can change no more than 0.26ns before the clock edge -- and that means that the data must be _valid_ at that point, not already meandering across the thresholds. It _doesn't_ mean that there's no hold time requirement at all -- just that the hold time requirement is a bit weird.

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Tim Wescott
Control system and signal processing consulting
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Reply to
Tim

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But then, that sounds very the same as the traditional setup time ???

Now its really weird & confuse. We have now two names to describe the same thing? and the same paper calls out 2 different numbers for the same thing

hmmm ???

Reply to
Mawa_fugo

No. You may change the data before, but not after, the setup time. You may change the data after the hold time, but not before it (i.e. not between the setup and hold time).

A small negative hold time can result from a delay internal to the FF on the data input, which is greater than any similar delay on the clock input.

There will be a window before this hold time (but after the setup time) during which you cannot change the data. SO if the hold time is -0.25ns, there will be a setup time of greater than 0.25ns, (e.g. 0.5ns) and a window between 0.5 and 0.25ns before the clock edge when the data must be stable.

This can be a deliberate design feature to guarantee that pipelines will avoid races in the presence of small amounts of clock skew, without having to specify minimum routing delays between pipe stages.

(Timing analysis will still have to guarantee maximum delays, for a particular clock frequency)

- Brian

Reply to
Brian Drummond

To be a little clearer, hold time is different from setup in that it defines the end of the data sampling window, while set defines the start of the window. What Tim meant by "no more than 0.26ns before the clock" is that the end of the valid window must not come *sooner* than 0.26 ns before the clock. So if the data is stable until 0.26 ns before the clock and *then* starts to change, you will sample the data in its stable state.

Negative numbers are a little perplexing because the definition of setup and hold are referenced in a different direction, based on the outdated assumption that a flip-flop's sampling window includes the clock edge. So for that case both setup and hold would be positive. For FPGA's, the actual data sampling window of a filp-flop is tiny, and the bulk of the setup and hold requirements are due to the delays in routing the signal and clock to the flip-flop's D and CLK inputs. Since either the clock or the data signal can have a longer routing delay, it's quite easy to end up with either negative set or negative hold times.

So think of it this way:

The clock arrives at time T. Data must be stable from time (T - setup) until time (T + hold). If setup is positive and hold is negative, then the stable window will be entirely before the clock edge: CLK --------T----------- Data xxxxxxxxxxxxxxx If hold is positive and setup is negative, the stable window will be entirely after the clock edge. CLK --------T----------- Data xxxxxxxxxxxxxxx If both setup and hold are positive, then the stable window includes the clock edge. CLK --------T----------- Data xxxxxxxxxxxxxxx

HTH, Gabor

Reply to
Gabor

Now, a chip that had both setup and hold times that were negative -- that would be astounding.

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Tim Wescott
Wescott Design Services
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Reply to
Tim Wescott

Kind of like precognitive sram. You get the data before you give it the address.

I've used asic libraries that were "0-Hold" time and all they do is tweak the timing with more delay in the D path than the C path. It's nice in that you don't have to fix hold times but most paths will have enough delay that a hold time fix is not needed. You then have to deal with the loss of setup time that affects all flops and this makes it harder to meet timing.

John

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Reply to
jt_eaton

ou

Sounds like everybody knows this but me... but now I think I can joint the group Thank you all very much, all the sudden I'm enlightenment, but please correct me if I'm still in darkness :-)))

This "negative hold time" (new to me) or whatever quantity, and the setup time the two points will define a time window, in which data can't be changed !

Reply to
Mawa_fugo

ak

you

a

up

But the concept "you get the data before you give the memory the address" is - not in my imagination

Reply to
Mawa_fugo

Correct.

It's a joke.

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Tim Wescott
Wescott Design Services
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Reply to
Tim Wescott

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