spartan2e block ram error

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consider the following code:

    (the rom is essentially a RAMB4_S1 block)
    -- rom
    ROM
        port map (
            CLK => Clock,                                        -- get data at rising edge
            ADDR => BUS_Address(11 downto 0),
            DATA => local_Data
        );

    debug <= local_Data;

    process(Reset, Clock, ChipSelect, BUS_WriteEnable) is
    begin
        if(Reset = '1') then
            BUS_DataOut <= (others => 'Z');
        elsif(falling_edge(Clock)) then                                -- present data at falling edge
            if(ChipSelect = '1' AND BUS_WriteEnable = '0') then
                BUS_DataOut <= local_Data;
            else
                BUS_DataOut <= (others => 'Z');
            end if;
        end if;
    end process;


when doing a simulate "post translate VHDL model" or simulate "post map",
everything works fine


when doing a simulate "post place and route vhdl model", it fails;
all my outputs are 'XX' and I get pages of the following warning:

 ** Warning: */X_RAMB4_S1 SETUP  Low VIOLATION ON ADDR(9) WITH RESPECT TO
CLK;
#   Expected := 1.04 ns; Observed := 0.12 ns; At : 6.7 ns
#    Time: 6700 ps  Iteration: 1  Instance: /testbench/uut/rom_inst5


any idea what is wrong? (I'd like to point out that in real life, it is
actually working, but I'd like to straighten it out in the simulator)

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