Despite trying all the read/write options on a Spartan 2 design I am moving to Spartan 3, The Spartan 3 BlockRAMS always seem to take one more clock to valid data output from a write from the other side.
I'm using ISE 6.3 and have tried inferring the RAMS with the VHDL source and using the core generator, no change.
Is there something fundamentally different between Spartan 2 and 3 blockRAMS timimg wise or is this a tool issue?
Pulling whats left of my hair out...
Peter Wallace