Spartan IIE VHDL inout port bidirectional bus problem.

Hi,

I am trying to use a bidirectional bus, declared as inout in my vhdl code. When running on FPGA eveything works, except that bus. The bus is dead all the time and can not be read.

I have tried changing that port to in only, and eveything works fine.

I understand that for an inout port, tristate needs to declared. Still, that doesn't help.

If anyone could please help out, it'd be much appreciated.

Thank you for your attention.

below is my code

--------------------------------------------------------------------------------

-- SubModule USB

-- Created 16/10/2005 6:51:41 PM

-------------------------------------------------------------------------------- Library IEEE; Use IEEE.Std_Logic_1164.all; use ieee.std_logic_unsigned.all;

entity USB is port ( PORTB : inout std_logic_vector(7 downto 0); CLK : in std_logic; RST : in std_logic; CS : in std_logic; DI : in std_logic_vector(7 downto 0); DO : out std_logic_vector(7 downto 0); A : in std_logic_vector(15 downto 0); WR : in std_logic; RD : in std_logic; IFCLK : in std_logic; FIFOADR : out std_logic_vector(1 downto 0); FLAGA : in std_logic; FLAGB : in std_logic; FLAGC : in std_logic; SLOE : out std_logic; SLRD : out std_logic; SLWR : out std_logic; PKTEND : out std_logic; RESET : out std_logic; WAIT_ST : out std_logic); end USB;

--------------------------------------------------------------------------------

-------------------------------------------------------------------------------- architecture behaviour of USB is

signal SLRD_buffer : std_logic; signal SLWR_buffer : std_logic; signal OE :std_logic;

begin

FIFOADR( 1 downto 0)

Reply to
liaobojie
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On 1 Nov 2005 18:17:45 -0800, snipped-for-privacy@gmail.com wrote: (..)

add these two lines:

library UNISIM; use UNISIM.VComponents.all;

add this line signal portb_in,portb_out:std_logic_vector(7 downto 0);

Reply to
Zara

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