I've just run a DDR2 based MIG through place and route and tried the simple= st of pin swaps, which failed. The default pinout is terrible for PCB routi= ng, does anyone know whether any swapping is possible if I drill down throu= gh the code. I had hoped that the hard silicon ddr core just made clock dom= ain control trivial, with the functional stuff still soft.
Has anyone tried this?
Cheers
Colin
of pin swaps, which failed. The default pinout is terrible for PCB routing, does anyone know whether any swapping is possible if I drill down through the code. I had hoped that the hard silicon ddr core just made clock domain control trivial, with the functional stuff still soft.
The core to IO routing is fixed. That being said there are some groups of pins that are swappable because they are equivalent. For example DQ pins within a byte can swap at the board level. Or you can swap the entire upper and lower DQ DM and DQS sets. Unfortunately you can't swap address pins. I can't think why you couldn't re-arrange the bank address pins, though. I seem to remember that there was an Answer Record discussing pins swapping with the MCB.
-- Gabor
of pin swaps, which failed. The default pinout is terrible for PCB routing, does anyone know whether any swapping is possible if I drill down through the code. I had hoped that the hard silicon ddr core just made clock domain control trivial, with the functional stuff still soft.
AFAIK you can't because the BA pins are also used during configuration to select the configuration register. Anyway, the routing of the address and control lines is way less critical than the data lines.
-- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------
simplest of pin swaps, which failed. The default pinout is terrible for PCB routing, does anyone know whether any swapping is possible if I drill down through the code. I had hoped that the hard silicon ddr core just made clock domain control trivial, with the functional stuff still soft.
O.K. - I found the answer record:
-- Gabor
It's not the best pinout but it can be routed on a 6 layer board as I have done it with a lx45 with two 16-bit DDR3 on either side of the device.
Jon
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Thanks for everyones replies. The last time, I had an 80 bit wide DDR2 interface to virtex 5 and I spent ages playing with the pinout so I suppose that Xilinx have saved me some time as I can't play.
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