Spartan 3E vs. Cyclone2

Hi,

I'm evaluating low cost FPGA's for a new design starting end next month.

Besides XC3S2000, EP1C20 and EC33 (I know, the EP1C20 is much smaller than the other 2), I was looking for other 90nm families. I found XC3S1500E, EP2C35, but no Lattice anymore.

I wonder about the availability of the XC3S1500E and EP2C35.

Has someone seen samples yet, knows something more how they compare (performance, pricewise). What about SW Tool support?

Regards,

Luc

Reply to
Luc
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Hi Luc,

EP1C20 is in full production, the EP2C35 is sampling with about a 4-week lead time if the disti's don't have any stock, the XC3S1500E has only been specced yet and I haven't got a clue about the Lattice part.

The EP2C35 will be more expensive than the EP1C20, with slightly higher performance in terms of routing and LE performance. The addition of HW multipliers is handy if you use them.

That's all I can say at the moment. Don't know how this all stacks up against X and L.

The EP1C20 is fully supported in Quartus, using final timing models, while the EP2C35 has preliminary support (i.e. no bitstream generation) in the standard version of Quartus 4.2. If you have a compelling reason to generate an EP2C35 bitstream right now there's ways to accomplish this already though. The EP2C35 will be fully supported in Quartus 5.0, released sometime end of April.

The XC3S1500E may already be supported in Webpack 7.1, but I'm not sure.

Best regards,

Ben

Reply to
Ben Twijnstra

Hi Luc,

I don't have much to add -- Ben has covered most of the high points.

On a performance front, you will find that Cyclone and Cyclone II have a significant performance advantage over Spartan-3. We're talking

50-60% (core performance on 100+ designs, comparing fastest speed grade to fastest speed grade using best-possible software settings).

But don't take my word on it. Download our freely available Quartus II Web Edition and give your design a whirl in Cyclone/Cyclone II. Do the same for Spartan-3.

Regards,

Paul Leventis Altera Corp.

Reply to
Paul Leventis

Ben & Paul,

Thanks for the feedback. I wonder what X & L could add to their defence.

What about DDR or DDR2 support? This is certainly somthing I'm looking for. Multipliers are benificial but not a necessity.

Regards,

Luc >Hi Luc,

Reply to
Luc

Well,

Suffice it to say, I don't agree with Paul, but that should come as no surprise.

Spartan 3S100E was just announced, so to ask if a 3S1500E is sampling is a bit like asking if we are ready to go visit Mars.

Seriously, announcement of the first available part usually means that the rest of the family is three to six months from even being taped out (for us, or Paul).

Announcement of the first part into production also means that the time till all parts are in production is out from three to six months (again, for us, or Paul).

Sometimes we do better than that. Sometimes they do better than that. Sometimes we both do worse. And suffer for it.

Depends on a lot of factors: are they any errata to fix? how many layer changes need to be made? is the process yielding? have we passed the process qualification? have we passed the product qualification? do we have parts ready to ship? so on and so forth.

For example: the 2S60 was announced as having received wafers on June

2, 2004.

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Then, they just recently admitted they will ship the final production version of that 2S60 part with the Iccint surge current fixed by the end of this month (3/31/2005). I am likely to believe this, as we just tested the 2S90, and the Iccint surge is all gone.

We announced the 4VLX25 on 6/28/2004 (lagging Altera, but we actually shipped five parts on boards on this date and the customer was USING them!).

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Then, we just recently announced we are shipping production on this part

1/31/2005:

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So, 9 months for a 2S60 from announcement of first wafer to production (unconfirmed, as it isn't 3/31 yet), and 7 months for the Xilinx 4VLX25 (confirmed).

Not much of a difference there.

If you go back and track every product announced, to every ES, to every product released to production, you will find a remarkably similar time line. After all, both Xilinx and Altera use world class fabs (UMC and TSMC), and both use a leading edge process, and the differences will be mostly related to factors that are totally random in nature (if we are going to be honest about it).

Go talk to your Xilinx FAE, and get the timeline for what you need.

Oh, and take the performance boasts (for these low cost parts) from everyone with a grain of salt. Until you see what your needs are, you are unlikely to be able to evaluate if there is even a difference in performance, and if that performance difference even matters for your application.

Sure, Spartan 3 (and 3E) have the 18X18 multipliers. And Altera has elements they are proud of in Cyclone 2.

But just like Virtex 4 vs Stratix 2, you are going to have to wade through a lot of very technical information if you are trying to compare benchmarks. Best you test your application, regardless.

Austin

Reply to
Austin Lesea

Luc,

Lattice EC/ECP are not 90nm, but 130nm at the 90nm cost. Excelent FGPA architecture, great DDR performance (400Mbs). Almost all the devices are available today. ispLEVER is free at the latticesemi.com

rgds,

cristian

Reply to
cas7406

BTW, the Cyclone manual says that the highest speed of an M4K RAM bank is 200MHz, but Quartus estimates it to about 250MHz (Cyclone 1C6, speed grade 6). So, which information is right?

Best regards Piotr Wyderski

Reply to
Piotr Wyderski

Hi Austin,

So this Mars Rover thing is all a lie? I knew the whole thing was fake, just like the moon landings! ;-)

Ben

Reply to
Ben Twijnstra

sampling is

fake, just

I'm going majorly off-topic here...

That reminds me of an mpeg clip I collected a while back: it has aliens on Mars holding up a print-out of a barren Martian landscape - so that's all the Mars rover can see. It's pretty funny... but I don't currently have anywhere to post it, and I can't find it online any more.

Marc

Reply to
Marc Randolph

Actually, that would be Actel -- not X or A -- devices supporting the Mars Rover ;)

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;)

cheers, Kris

Reply to
Kris Vorwerk

Kris,

Well, we are in the wheel control, arm control, and we did the pyro control for the lander:

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Austin

Reply to
austin

Always trust the latest version of Quartus -- the datasheet is supposed to follow whatever we put in the software, not vice versa. I will check into this and get the datasheet corrected if neccessary.

Regards,

Paul Leventis Altera Corp.

Reply to
Paul Leventis (at home)

Hi Luc,

I don't have definite specs handy, but Cyclone 1 can control DDR SDRAM at

133MHz (see the Twister board at
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The device chosen was a 240-pin QFP, which caused the PCB and FPGA designer some headaches to meet timing. Had he been allowed to use an F256 device, things would have been a lot easier.

The Cyclone and Cyclone II will do both DDR and DDR2. I'd personally just go for DDR using a Cyclone(II) in an FPBGA package - this mainly due to availability of DDR chips compared to DDR2 chips and ease of design in the FPGA.

BTW: the Cyclone II multipliers are currently rated at 250MHz. I have a standing bet (6 beers) that production silicon will be fast enough to reach something in bthe range of 270-320MHz, and I'm not expecting to give out any beer.

Best regards,

Ben

Reply to
Ben Twijnstra

Yes, I have seen the same specification and I wonder why it is so slow. I have some SDR memories with fmax = 183MHz, so I would like to know whether it is possible to use them with a Cyclone at that speed. The next problem is that the data path width will be 48 bits and the megafunction documentation says that the controller is capable of doing 16-, 32- and 64-bit transfers. But how about 48 bits? :-)

Best regards Piotr Wyderski

Reply to
Piotr Wyderski

It comes from a long and god tradition though - there have been ones with for example martians "manning" large fans to create dust storms to hinder poor earth-sent satellites ;-)

--
	Sander

+++ Out of cheese error +++
Reply to
Sander Vesik

When we are talking about IO: Does anybody (i.e. Austin ;-) know the max. LVDS-transmit-rate of Spartan 3E, slowest speed-grade?

Regards,

Thomas

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"Luc" schrieb im Newsbeitrag news: snipped-for-privacy@4ax.com...

Reply to
Thomas Entner

Thomas,

The maximum speed of the LVDS buffers is a good question for me to try to shed some light on in this forum.

The LVDS buffers (both input, and output) are built from the 0.25 micron gate oxide transistors we use for IO in all devices since Virtex II Pro. These same devices are used for the 3.125 Gbs MGT front ends, so the transistors themselves are extremely quick.

But, it is all in the sizing, and a regular IO is burdened by having to support 34 other IO standards. These LVDS IOs were not designed to work beyond 1 Gbs. Not that we did anything intentional to make them slow, we just didn't model them at all corners above 1 Gbs because is was not a requirement. As such, the interconnect and logic is not sized for Gbs speeds, either into, or out of, the IOB.

Why isn't it a requirement? Well, the fabric can't handle it anyway.

By that, I mean it is not the IO that is the limiting factor for any given standard. Take Aurora, or SPI POS 4.X, or some other IO protocol and signalling 'standard' for example. You must have a clock synchronization system, data multiplexing/demultiplexing that meets the standard. And also a core with the state maqchines, CRC, BRAM FIFO's, etc.

In Virtex 4 (my favorite subject) we have the Source Synchronous IO blocks for every I/O pin which is a serdes for each pin: this easily matches Gbs speeds on DDR IO pins to the fabric at 1/2, 1/4, 1/8 (etc) speeds along with allowing for fixed or dyanamic bit eye slicing to get the best possible link. That hardware is definitely limited by the LVDS. The LVDS in V4 is running at 1.4 to 1.5 Gbs (spec'd at 1 Gbs), but we haven't characterized it over all corners, voltage and temperatures. We just may, but only after we have the entire interface designed to support it.

No reason to have fast IO if there is nothing to support it. The opposite is also true, a fast core is useless without the fast IO.

Basically, if you want Gbs performance, we have a cost effective part for that, the Virtex 4. Spartan 3 and 3E (identical 90nm technologies) are intended for large volume low cost applications below ~300 MHz global clock speeds.

The triple oxide technology in V4 provices us with a substantial increase in interconnect performance required for 500 MHz clocked logic. Spartan 3 and 3E don't have that Ace up their sleeves.

Spartan 3, and 3E are intended to address the best IO/$, and the best logic/$ sockets. I would not distinguish between them on the basis of performance or speed: they represent vitually identical devices cost optimized for the two different application spaces (logic vs. IO).

Aust> When we are talking about IO: Does anybody (i.e. Austin ;-) know the max.

Reply to
austin

Really off-topic,

Since we are on the rovers, (the Virtex 1000's, 12 on each rover), I watched the JPL website every day in the early days after landing.

One day, I missed looking at the downloads.

The next day, one of the pictures had a set of Mickey Mouse Ears on it!

Wow! Was I impressed? Do they watch the Disney Channel up there?

Turns out the grinding tool had ground out three circles the day before, creating the classic set of 'ears.'

Austin

Reply to
austin

It looks like the closest alternative for the EP2C35 is the XC3S1500 or the EC33 (I don't need the multipliers). The first two, real 90nm parts, the last a 130nm devices at 90nm price.

I was looking at implementing a DDR400 or DDR333 interface, and according to the different datasheets and the posting, only the ECP33 will be able to support this. This makes the choise not so obvious. But probably I can live with DDR266.

I guess, some discussions with my local distis and a short evaluation will bring the solution.

Thanks for your posts,

Luc

Reply to
Luc

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Reply to
leonqin

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